1
0
mirror of https://github.com/aolofsson/oh.git synced 2025-01-17 20:02:53 +08:00
oh/etrace
Andreas Olofsson d9f18e7b58 DV cleanup
-removing all redundant build files, there must be only one...
2016-03-08 21:23:02 -05:00
..
2016-03-08 21:23:02 -05:00
2016-02-26 19:08:40 -05:00
2015-11-25 21:30:10 -05:00

ETRACE INTRODUCTION

The "etrace" module is a simple parametrized logic analyzer that captures a set of input signals in dual ported memory. Captured values can be read out through a memory mapped interface. Each sampled value is stored together with a counter time stamp. The vector is sampled on the rising edge of "trace_clk".

USAGE

  1. Instantiate in block and hook up signals. Use the dv/dut_etrace.v as an example

  2. Enable the tracer by setting the trace_trigger to high AND setting bit[0] of the ETRACE_CFG register(810F00000).

  3. (sample signals for as long as you want)

  4. Read back values through the mi interface: 810A00000,810A00004,etc