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131 lines
3.7 KiB
Verilog
131 lines
3.7 KiB
Verilog
module mrx (/*AUTOARG*/
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// Outputs
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rx_wait, access_out, packet_out,
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// Inputs
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clk, nreset, datasize, rx_clk, rx_access, rx_packet, wait_in
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);
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//#####################################################################
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//# INTERFACE
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//#####################################################################
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//parameters
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parameter PW = 104; // data width (core)
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parameter MIOW = 8; // IO data width
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parameter FIFO_DEPTH = 32; // fifo depth
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localparam CW = $clog2(2*PW/MIOW);// transfer count width
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//reset, clk
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input clk; // main core clock
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input nreset; // async active low reset
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//rx config
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input [CW-1:0] datasize; // size of data transmitted
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//delay, enable?
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//IO interface
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input rx_clk; // clock from IO
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input rx_access; // access signal for IO
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input [MIOW-1:0] rx_packet; // packet from IO
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output rx_wait; // pushback for IO
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// data
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output access_out; // fifo data valid
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output [PW-1:0] packet_out; // fifo packet
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input wait_in; // wait pushback for fifo
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//#####################################################################
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//# BODY
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//#####################################################################
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/*AUTOOUTPUT*/
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire fifo_access; // From mrx_protocol of mrx_protocol.v
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wire [PW-1:0] fifo_packet; // From mrx_protocol of mrx_protocol.v
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wire io_access; // From mrx_io of mrx_io.v
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wire [2*MIOW-1:0] io_packet; // From mrx_io of mrx_io.v
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// End of automatics
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//########################################
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//# SYNCHRONIZATION FIFO
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//########################################
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/*oh_fifo_cdc AUTO_TEMPLATE (
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.wait_out (rx_wait),
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.access_out (access_out),
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.packet_out (packet_out[PW-1:0]),
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// Inputs
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.nreset (nreset),
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.clk_in (rx_clk),
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.access_in (fifo_access),
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.packet_in (fifo_packet[PW-1:0]),
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.clk_out (clk),
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.wait_in (wait_in),
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);
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*/
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oh_fifo_cdc #(.DW(PW),
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.DEPTH(FIFO_DEPTH))
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fifo (/*AUTOINST*/
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// Outputs
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.wait_out (rx_wait), // Templated
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.access_out (access_out), // Templated
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.packet_out (packet_out[PW-1:0]), // Templated
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// Inputs
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.nreset (nreset), // Templated
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.clk_in (rx_clk), // Templated
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.access_in (fifo_access), // Templated
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.packet_in (fifo_packet[PW-1:0]), // Templated
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.clk_out (clk), // Templated
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.wait_in (wait_in)); // Templated
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//########################################
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//# PROTOCOL
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//########################################
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/*mrx_protocol AUTO_TEMPLATE (
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.clk (rx_clk),
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);
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*/
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mrx_protocol #(.PW(PW),
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.MIOW(MIOW))
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mrx_protocol (/*AUTOINST*/
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// Outputs
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.fifo_access (fifo_access),
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.fifo_packet (fifo_packet[PW-1:0]),
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// Inputs
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.clk (rx_clk), // Templated
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.nreset (nreset),
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.datasize (datasize[CW-1:0]),
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.io_access (io_access),
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.io_packet (io_packet[2*MIOW-1:0]));
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//########################################
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//# FAST IO (DDR)
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//########################################
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/*mrx_io AUTO_TEMPLATE (
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.clk (rx_clk),
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);
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*/
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mrx_io #(.MIOW(MIOW))
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mrx_io (
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/*AUTOINST*/
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// Outputs
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.io_access (io_access),
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.io_packet (io_packet[2*MIOW-1:0]),
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// Inputs
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.nreset (nreset),
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.clk (rx_clk), // Templated
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.rx_packet (rx_packet[MIOW-1:0]),
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.rx_access (rx_access));
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endmodule // ctx
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// Local Variables:
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// verilog-library-directories:("." "../../common/hdl")
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// End:
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