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59 lines
2.1 KiB
Tcl
59 lines
2.1 KiB
Tcl
set pwd [file dirname [info script]]
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source $pwd/../../../include/oh.tcl
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#ONLY FOR REFERENCE EXAMPLE
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read_verilog $top_srcdir/elink/hdl/axi_elink.v
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#ELINK
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read_verilog $top_srcdir/elink/hdl/elink_constants.v
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read_verilog $top_srcdir/elink/hdl/elink_regmap.v
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read_verilog $top_srcdir/elink/hdl/elink.v
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read_verilog $top_srcdir/elink/hdl/eclocks.v
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read_verilog $top_srcdir/elink/hdl/ereset.v
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read_verilog $top_srcdir/elink/hdl/ecfg_elink.v
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read_verilog $top_srcdir/elink/hdl/ecfg_if.v
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read_verilog $top_srcdir/elink/hdl/erx.v
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read_verilog $top_srcdir/elink/hdl/erx_core.v
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read_verilog $top_srcdir/elink/hdl/erx_fifo.v
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read_verilog $top_srcdir/elink/hdl/erx_cfg.v
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read_verilog $top_srcdir/elink/hdl/erx_arbiter.v
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read_verilog $top_srcdir/elink/hdl/erx_protocol.v
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read_verilog $top_srcdir/elink/hdl/erx_remap.v
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read_verilog $top_srcdir/elink/hdl/erx_io.v
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read_verilog $top_srcdir/elink/hdl/etx.v
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read_verilog $top_srcdir/elink/hdl/etx_core.v
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read_verilog $top_srcdir/elink/hdl/etx_fifo.v
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read_verilog $top_srcdir/elink/hdl/etx_cfg.v
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read_verilog $top_srcdir/elink/hdl/etx_arbiter.v
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read_verilog $top_srcdir/elink/hdl/etx_protocol.v
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read_verilog $top_srcdir/elink/hdl/etx_remap.v
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read_verilog $top_srcdir/elink/hdl/etx_io.v
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read_verilog $top_srcdir/elink/hdl/esaxi.v
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read_verilog $top_srcdir/elink/hdl/emaxi.v
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#COMMON
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read_verilog $top_srcdir/common/hdl/toggle2pulse.v
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read_verilog $top_srcdir/common/hdl/synchronizer.v
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read_verilog $top_srcdir/common/hdl/pulse_stretcher.v
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read_verilog $top_srcdir/common/hdl/clock_divider.v
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read_verilog $top_srcdir/common/hdl/arbiter_priority.v
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#EMESH
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read_verilog $top_srcdir/emesh/hdl/emesh2packet.v
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read_verilog $top_srcdir/emesh/hdl/packet2emesh.v
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#MEMORY/FIFO
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read_verilog $top_srcdir/memory/hdl/fifo_async.v
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read_verilog $top_srcdir/memory/hdl/fifo_sync.v
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read_verilog $top_srcdir/memory/hdl/fifo_cdc.v
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read_verilog $top_srcdir/memory/hdl/memory_dp.v
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read_verilog $top_srcdir/memory/hdl/memory_sp.v
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read_verilog $top_srcdir/memory/hdl/fifo_full_block.v
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read_verilog $top_srcdir/memory/hdl/fifo_empty_block.v
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#MMU
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read_verilog $top_srcdir/emmu/hdl/emmu.v
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read_verilog $top_srcdir/emailbox/hdl/emailbox.v
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read_verilog $top_srcdir/edma/hdl/edma.v
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