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178 lines
4.0 KiB
Markdown
178 lines
4.0 KiB
Markdown
---- ----
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name: Creating an FPGA accelerator in 15 min
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---- #Title ----
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background-image: /images/parallella_front_slant.png
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----
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## Creating an FPGA accelerator in 15 min!
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Andreas Olofsson, Adapteva & Parallella Founder
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(Presented at ANL FPGA Workshop)
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---- #parallella-introduction ----
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background-image: /images/parallella_front_slant.png
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## Kickstarting Parallel Computing
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* Parallella: "Supercomputing for everyone"
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* 18 CPU cores + FPGA on a credit card (5W)
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* Democratizes access to parallel computing
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* $898K raised on Kickstarter in Oct 2012
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* Open source and open access
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* Starting at $99
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* Available at Amazon & Digi-Key
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---- #parallella-specs ----
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## Parallella Specs (http://parallella.org)
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|---------------------- |:----------------------:|
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| Performance | ~30 GFLOPS |
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| Architecture | ARM + FPGA + MANYCORE |
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| Memory | 1GB DDR3 |
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| IO | ~25 Gb/s (48 GPIO) |
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| Size | credit-card |
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| Power | <5W |
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| Cost | $99 -> $249 |
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---- #Software ----
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## "Hello World" in Software
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1. **CODE:** main() { printf("Hello World\n");}
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2. **COMPILE:** gcc hello.c
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3. **TEST:** ./a.out
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3. **DEBUG:** printf, gdb
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---- #Hardware ----
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## "Hello World" in Hardware
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1. **CODE:** Verilog/VHDL source
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2. **CODE MORE:** Verilog/SystemC testbench
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3. **TEST:** VCS/NC/Icarus/Verilator
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4. **DEBUG:** Waveform debugging
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5. **SYNTHESIZE:** HDL-->NETLIST-->POLYGONS
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6. **BURN:** FPGA/ASIC
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7. **TEST MORE:** Pray that it works...
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---- #Comparison ----
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## Hardware vs Software
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| | SW | HW |
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|---------------- |:----------:|:---------------:|
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| Compile Time | seconds | minutes/months |
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| Libraries | lots | little |
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| Debugging | "easy" | an art |
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| Cost of mistake | low | VERY HIGH!!!! |
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---- #start ----
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## Let's start..."hello world"
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```verilog
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assign result[31:0]=input0[31:0]+input1[31:0];
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```
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> Now what??
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---- #Steps ----
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## What's missing
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1. Control code
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2. Host/Accelerator Hardware interfaces
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3. Test environment
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4. Synthesis scripts (non trivial)
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5. Drivers (software)
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> How many man-years is that?
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---- #OH ----
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## OH! (Open Hardware Library)
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* Verilog
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* MIT license
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* ~15K lines of code so far
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* Best practices based on 20 years of chip design
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* Silicon proven building blocks
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* **Small:** FIFOs, synchronizers, muxes, arbiters, etc
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* **Big:** chip to chip link, mailboxes, memory translators
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* http://github.com/parallella/oh
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* Yes, we do accept pull requests!
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---- #DEMO ----
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background-image: /images/parallella_front_slant.png
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## DEMO
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---- #Summary ----
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## Accelerator Case Study
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1. **Coding:** 2hrs
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2. **Simulate/Debug:** 2hrs
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3. **Synthesize:** 2hrs
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4. **Debug 1st "Bus Error":** 1hr
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5. **Debug 2nd "Bus Error":** 2hrs
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> 9hrs to put together something that takes 30 seconds in C!
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---- #Files ----
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## Files Used
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SOURCES: http://github.com/parallella/oh
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1. **Code:** hdl/{accelerator.v,axi_accelerator.v}
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2. **Testbench:** dv/{dut_axi_accelerator.v,build.sh,run.sh}
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3. **Synthesis:** fpga/{package.tcl, run.tcl}
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4. **Drivers:** sw/{driver.c,test.c}
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---- #How-To ----
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## How to Verify, Modify, and Burn
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```sh
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$ cd accelerator/dv
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$ ./build.sh # build
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$ ./run.sh tests/hello.emf # load data
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$ gtkwave waveform.vcd # view waveform
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$ emacs ../hdl/accelerator.v # "put code here"
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$ cd ../fpga
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$ ./build.sh # build bitstream
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$ sudo cp parallella.bit.bin /media/$user/boot
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$ sync #Insert SD card in parallella
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```
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---- #Conclusions ----
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## Conclusions
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1. Yes, today you CAN build an FPGA accelerator in 15 min
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2. Anything new is still 100x more expensive to develop than SW
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3. Develop for FPGAs, but keep ASIC option open
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> ...to make FPGA universally viable we need to catch up with >>$trillion investment in software infrastructure
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**Email:** andreas@adapteva.com
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**Twitter:** @adapteva
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