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91f8e3db5a
- After finding the bug in the reference model and wasting countless hours going back and forth with FPGA timing optimization and bug tweaks, I realized that the design was fundementally broken. The decision to use two clock domains (high speed) and low speed was correct from the beginning. The FPGA is dreadfully slow, (you definitely don't want to do much logic at 300MHz...), but the handoff between tclk and tclk_div4 was too complicated. The puzzle of having to respond to wait quickly, covering the corner cases, and meeting timing was just too ugly. - The "new" design goes back to the method of using the high speed logic only for doing a "dumb" parallel to serial converter and preparing all the necessary signals in the low speed domain. - This feel A LOT cleaner and the it already passes basic tests with the chip reference and the loopback after less than 3 hours of redesign work! - The TX meets timing but there is still some work to do with wait pushback testing.
75 lines
1.9 KiB
Verilog
75 lines
1.9 KiB
Verilog
module etx_remap (/*AUTOARG*/
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// Outputs
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emesh_access_out, emesh_packet_out,
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// Inputs
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clk, emesh_access_in, emesh_packet_in, remap_en, remap_bypass,
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etx_rd_wait, etx_wr_wait
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);
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parameter AW = 32;
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parameter DW = 32;
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parameter PW = 104;
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//Clock
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input clk;
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//Input from arbiter
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input emesh_access_in;
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input [PW-1:0] emesh_packet_in;
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input remap_en; //enable tx remap (static)
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input remap_bypass; //dynamic control (read request)
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//Output to TX IO
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output emesh_access_out;
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output [PW-1:0] emesh_packet_out;
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//Wait signals from protocol block
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input etx_rd_wait;
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input etx_wr_wait;
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wire [31:0] addr_in;
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wire [31:0] addr_remap;
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wire [31:0] addr_out;
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wire write_in;
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reg emesh_access_out;
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reg [PW-1:0] emesh_packet_out;
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packet2emesh p2e (// Outputs
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.write_out (write_in),
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.datamode_out (),
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.ctrlmode_out (),
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.data_out (),
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.dstaddr_out (addr_in[31:0]),
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.srcaddr_out (),
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// Inputs
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.packet_in (emesh_packet_in[PW-1:0]));
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assign addr_remap[31:0] = {addr_in[29:18],//ID
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addr_in[17:16],//SPECIAL GROUP
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{(2){(|addr_in[17:16])}},//ZERO IF NOT SPECIAL
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addr_in[15:0]
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};
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assign addr_out[31:0] = (remap_en & ~remap_bypass) ? addr_remap[31:0] :
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addr_in[31:0];
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//stall read/write access appropriately
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always @ (posedge clk)
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if(~(etx_wr_wait | etx_rd_wait))
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begin
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emesh_access_out <= emesh_access_in;
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emesh_packet_out[PW-1:0] <= {emesh_packet_in[PW-1:40],
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addr_out[31:0],
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emesh_packet_in[7:0]
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};
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end
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endmodule // etx_remap
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// Local Variables:
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// verilog-library-directories:("." "../../emesh/hdl")
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// End:
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