FPGA/oh

mirror of https://github.com/aolofsson/oh.git synced 2025-01-17 20:02:53 +08:00

Andreas.Olofsson d6f5de24d7 Changing hierarchy to promote blocks

2020-01-28 18:12:57 -05:00

241 B

Raw Blame History

What defines are used

iverilog -g2005 -DTARGET_SIM=1 $cfg $core.v $DV -f $LIBS -o $core.bin

How to compile all duts?

The script "build_all.sh" builds all dut files in this directory with random

./build_all.sh