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40 lines
1.3 KiB
Verilog
40 lines
1.3 KiB
Verilog
//#############################################################################
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//# Function: BCD Seven Segment Decoderh #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_7seg_decode ( input [3:0] bcd, //0-9
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output a, //a segment (1=0ff)
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output b, //b segment
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output c, //c segment
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output d, //d segment
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output e, //e segment
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output f, //f segment
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output g //g segment
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);
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reg a,b,c,d,e,f,g;
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always @ (*)
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case(bcd[3:0])
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4'h0 : {a,b,c,d,e,f,g} = 7'b0000001;
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4'h1 : {a,b,c,d,e,f,g} = 7'b1001111;
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4'h2 : {a,b,c,d,e,f,g} = 7'b0010010;
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4'h3 : {a,b,c,d,e,f,g} = 7'b0000110;
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4'h4 : {a,b,c,d,e,f,g} = 7'b1001100;
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4'h5 : {a,b,c,d,e,f,g} = 7'b0100100;
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4'h6 : {a,b,c,d,e,f,g} = 7'b0100000;
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4'h7 : {a,b,c,d,e,f,g} = 7'b0001111;
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4'h8 : {a,b,c,d,e,f,g} = 7'b0000000;
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4'h9 : {a,b,c,d,e,f,g} = 7'b0001100;
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default : {a,b,c,d,e,f,g} = 7'b1111111;
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endcase // case (in[3:0])
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endmodule
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