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49 lines
1.3 KiB
Verilog
49 lines
1.3 KiB
Verilog
//#############################################################################
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//# Function: Carry Save Adder (4:2) #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_csa42 #( parameter DW = 1 // data width
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)
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( input [DW-1:0] in0, //input
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input [DW-1:0] in1,//input
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input [DW-1:0] in2,//input
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input [DW-1:0] in3,//input
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input cin,//intra stage carry in
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output cout, //intra stage carry out (2x sum)
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output [DW-1:0] s, //sum
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output [DW-1:0] c //carry (2x sum)
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);
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wire [DW-1:0] sum_int;
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wire [DW:0] carry_int;
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//Edges
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assign cout = carry_int[DW];
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//Full Adders
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oh_csa32 #(.DW(DW))
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fa0 (//inputs
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.in0(in0[DW-1:0]),
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.in1(in1[DW-1:0]),
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.in2(in2[DW-1:0]),
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//outputs
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.c(carry_int[DW:1]),
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.s(sum_int[DW-1:0]));
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oh_csa32 #(.DW(DW))
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fa1 (//inputs
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.in0(in3[DW-1:0]),
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.in1(sum_int[DW-1:0]),
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.in2({carry_int[DW-1:1],cin}),
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//outputs
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.c(c[DW-1:0]),
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.s(s[DW-1:0]));
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endmodule // oh_csa42
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