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8b39f7e444
-Changing DW to RW (RW not always equal to DW..) -Blocking rd_data on valid -Fixing elemetary bugs based on indices -Simplifying index code -Add configurable pipeline stage?
55 lines
1.7 KiB
Verilog
55 lines
1.7 KiB
Verilog
//#############################################################################
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//# Function: Parametrized register file #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_regfile # (parameter REGS = 32, // number of registeres
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parameter RW = 64, // register width
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parameter RP = 5, // read ports
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parameter WP = 3 // write prots
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)
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(//Control inputs
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input clk,
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input nreset,
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// Write Ports (concatenated)
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input [WP-1:0] wr_valid, // write access
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input [WP*RAW-1:0] wr_addr, // register address
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input [WP*RW-1:0] wr_data, // write data
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// Read Ports (concatenated)
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input [RP-1:0] rd_valid, // read access
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input [RP*RAW-1:0] rd_addr, // register address
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output [RP*RW-1:0] rd_data // output data
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);
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localparam RAW = $clog2(REGS);
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genvar i;
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reg [RW-1:0] mem [0:REGS-1];
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//TODO: Make an array of cells
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//#########################################
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// write ports
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//#########################################
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for (i=0;i<WP;i=i+1)
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always @ (posedge clk)
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if (wr_valid[i])
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mem[wr_addr[(i+1)*RAW-1:i*RAW]] <= wr_data[(i+1)*RW-1:i*RW];
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//#########################################
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// read ports
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//#########################################
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for (i=0;i<RP;i=i+1)
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assign rd_data[i*RW+:RW] = {(RW){rd_valid[i]}} &
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mem[rd_addr[i*RAW+:RAW]];
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endmodule // oh_regfile
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