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0a2ea66b7e
- would only show up at different ID - better to always make defauly nonsense - sneaky...
403 lines
15 KiB
Verilog
403 lines
15 KiB
Verilog
module axi_elink(/*AUTOARG*/
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// Outputs
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timeout, elink_active, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p,
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rxo_rd_wait_n, txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n,
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txo_data_p, txo_data_n, chipid, chip_nreset, cclk_p, cclk_n,
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mailbox_not_empty, mailbox_full, m_axi_awid, m_axi_awaddr,
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m_axi_awlen, m_axi_awsize, m_axi_awburst, m_axi_awlock,
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m_axi_awcache, m_axi_awprot, m_axi_awqos, m_axi_awvalid, m_axi_wid,
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m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid, m_axi_bready,
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m_axi_arid, m_axi_araddr, m_axi_arlen, m_axi_arsize, m_axi_arburst,
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m_axi_arlock, m_axi_arcache, m_axi_arprot, m_axi_arqos,
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m_axi_arvalid, m_axi_rready, s_axi_arready, s_axi_awready,
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s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_rid, s_axi_rdata,
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s_axi_rlast, s_axi_rresp, s_axi_rvalid, s_axi_wready,
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// Inputs
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sys_nreset, sys_clk, rxi_lclk_p, rxi_lclk_n, rxi_frame_p,
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rxi_frame_n, rxi_data_p, rxi_data_n, txi_wr_wait_p, txi_wr_wait_n,
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txi_rd_wait_p, txi_rd_wait_n, m_axi_aresetn, m_axi_awready,
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m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid, m_axi_arready,
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m_axi_rid, m_axi_rdata, m_axi_rresp, m_axi_rlast, m_axi_rvalid,
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s_axi_aresetn, s_axi_arid, s_axi_araddr, s_axi_arburst,
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s_axi_arcache, s_axi_arlock, s_axi_arlen, s_axi_arprot,
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s_axi_arqos, s_axi_arsize, s_axi_arvalid, s_axi_awid, s_axi_awaddr,
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s_axi_awburst, s_axi_awcache, s_axi_awlock, s_axi_awlen,
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s_axi_awprot, s_axi_awqos, s_axi_awsize, s_axi_awvalid,
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s_axi_bready, s_axi_rready, s_axi_wid, s_axi_wdata, s_axi_wlast,
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s_axi_wstrb, s_axi_wvalid
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);
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parameter AW = 32;
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parameter DW = 32;
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parameter PW = 104; //packet width
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parameter ID = 12'h810;
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parameter S_IDW = 12; //ID width for S_AXI
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parameter M_IDW = 6; //ID width for M_AXI
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parameter IOSTD_ELINK = "LVDS_25";
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parameter ETYPE = 0;
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/****************************/
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/*CLK AND RESET */
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/****************************/
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input sys_nreset; // active low async reset
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input sys_clk; // system clock for AXI
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output elink_active; // link is active and ready
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/********************************/
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/*ELINK I/O PINS */
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/********************************/
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//Receiver
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input rxi_lclk_p, rxi_lclk_n; //link rx clock input
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input rxi_frame_p, rxi_frame_n; //link rx frame signal
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input [7:0] rxi_data_p, rxi_data_n; //link rx data
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output rxo_wr_wait_p,rxo_wr_wait_n; //link rx write pushback output
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output rxo_rd_wait_p,rxo_rd_wait_n; //link rx read pushback output
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//Transmitter
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output txo_lclk_p, txo_lclk_n; //link tx clock output
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output txo_frame_p, txo_frame_n; //link tx frame signal
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output [7:0] txo_data_p, txo_data_n; //link tx data
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input txi_wr_wait_p,txi_wr_wait_n; //link tx write pushback input
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input txi_rd_wait_p,txi_rd_wait_n; //link tx read pushback input
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/********************************/
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/*EPIPHANY INTERFACE (I/O PINS) */
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/********************************/
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output [11:0] chipid; //chip id strap pins for Epiphany
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output chip_nreset; //chip reset for Epiphany (active low)
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output cclk_p,cclk_n; //high speed clock (up to 1GHz) to Epiphany
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/*****************************/
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/*MAILBOX (interrupts) */
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/*****************************/
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output mailbox_not_empty;
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output mailbox_full;
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//########################
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//AXI MASTER INTERFACE
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//########################
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input m_axi_aresetn; // global reset singal.
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//Write address channel
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output [M_IDW-1:0] m_axi_awid; // write address ID
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output [31 : 0] m_axi_awaddr; // master interface write address
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output [7 : 0] m_axi_awlen; // burst length.
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output [2 : 0] m_axi_awsize; // burst size.
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output [1 : 0] m_axi_awburst; // burst type.
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output m_axi_awlock; // lock type
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output [3 : 0] m_axi_awcache; // memory type.
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output [2 : 0] m_axi_awprot; // protection type.
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output [3 : 0] m_axi_awqos; // quality of service
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output m_axi_awvalid; // write address valid
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input m_axi_awready; // write address ready
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//Write data channel
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output [M_IDW-1:0] m_axi_wid;
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output [63 : 0] m_axi_wdata; // master interface write data.
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output [7 : 0] m_axi_wstrb; // byte write strobes
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output m_axi_wlast; // last transfer in a write burst.
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output m_axi_wvalid; // indicates data is ready to go
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input m_axi_wready; // slave is ready for data
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//Write response channel
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input [M_IDW-1:0] m_axi_bid;
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input [1 : 0] m_axi_bresp; // status of the write transaction.
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input m_axi_bvalid; // valid write response
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output m_axi_bready; // master can accept write response.
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//Read address channel
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output [M_IDW-1:0] m_axi_arid; // read address ID
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output [31 : 0] m_axi_araddr; // initial address of a read burst
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output [7 : 0] m_axi_arlen; // burst length
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output [2 : 0] m_axi_arsize; // burst size
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output [1 : 0] m_axi_arburst; // burst type
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output m_axi_arlock; // lock type
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output [3 : 0] m_axi_arcache; // memory type
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output [2 : 0] m_axi_arprot; // protection type
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output [3 : 0] m_axi_arqos; // --
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output m_axi_arvalid; // read address and control is valid
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input m_axi_arready; // slave is ready to accept an address
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//Read data channel
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input [M_IDW-1:0] m_axi_rid;
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input [63 : 0] m_axi_rdata; // master read data
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input [1 : 0] m_axi_rresp; // status of the read transfer
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input m_axi_rlast; // signals last transfer in a read burst
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input m_axi_rvalid; // signaling the required read data
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output m_axi_rready; // master can accept the readback data
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/*****************************/
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/*AXI slave interface */
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/*****************************/
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//Clock and reset
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input s_axi_aresetn;
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//Read address channel
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input [S_IDW-1:0] s_axi_arid; //write address ID
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input [31:0] s_axi_araddr;
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input [1:0] s_axi_arburst;
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input [3:0] s_axi_arcache;
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input s_axi_arlock;
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input [7:0] s_axi_arlen;
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input [2:0] s_axi_arprot;
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input [3:0] s_axi_arqos;
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output s_axi_arready;
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input [2:0] s_axi_arsize;
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input s_axi_arvalid;
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//Write address channel
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input [S_IDW-1:0] s_axi_awid; //write address ID
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input [31:0] s_axi_awaddr;
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input [1:0] s_axi_awburst;
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input [3:0] s_axi_awcache;
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input s_axi_awlock;
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input [7:0] s_axi_awlen;
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input [2:0] s_axi_awprot;
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input [3:0] s_axi_awqos;
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input [2:0] s_axi_awsize;
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input s_axi_awvalid;
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output s_axi_awready;
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//Buffered write response channel
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output [S_IDW-1:0] s_axi_bid; //write address ID
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output [1:0] s_axi_bresp;
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output s_axi_bvalid;
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input s_axi_bready;
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//Read channel
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output [S_IDW-1:0] s_axi_rid; //write address ID
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output [31:0] s_axi_rdata;
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output s_axi_rlast;
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output [1:0] s_axi_rresp;
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output s_axi_rvalid;
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input s_axi_rready;
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//Write channel
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input [S_IDW-1:0] s_axi_wid; //write address ID
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input [31:0] s_axi_wdata;
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input s_axi_wlast;
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input [3:0] s_axi_wstrb;
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input s_axi_wvalid;
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output s_axi_wready;
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/*#############################################*/
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/* END OF BLOCK INTERFACE */
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/*#############################################*/
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/*AUTOINPUT*/
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/*AUTOOUTPUT*/
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// Beginning of automatic outputs (from unused autoinst outputs)
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output timeout; // From elink of elink.v
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// End of automatics
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// End of automatics
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire rxrd_access; // From elink of elink.v
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wire [PW-1:0] rxrd_packet; // From elink of elink.v
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wire rxrd_wait; // From emaxi of emaxi.v
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wire rxrr_access; // From elink of elink.v
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wire [PW-1:0] rxrr_packet; // From elink of elink.v
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wire rxrr_wait; // From esaxi of esaxi.v
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wire rxwr_access; // From elink of elink.v
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wire [PW-1:0] rxwr_packet; // From elink of elink.v
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wire rxwr_wait; // From emaxi of emaxi.v
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wire txrd_access; // From esaxi of esaxi.v
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wire [PW-1:0] txrd_packet; // From esaxi of esaxi.v
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wire txrd_wait; // From elink of elink.v
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wire txrr_access; // From emaxi of emaxi.v
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wire [PW-1:0] txrr_packet; // From emaxi of emaxi.v
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wire txrr_wait; // From elink of elink.v
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wire txwr_access; // From esaxi of esaxi.v
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wire [PW-1:0] txwr_packet; // From esaxi of esaxi.v
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wire txwr_wait; // From elink of elink.v
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// End of automatics
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//########################################################
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//ELINK
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//########################################################
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defparam elink.IOSTD_ELINK = IOSTD_ELINK;
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defparam elink.ETYPE = ETYPE;
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defparam elink.ID = ID;
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elink elink(
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/*AUTOINST*/
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// Outputs
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.elink_active (elink_active),
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.rxo_wr_wait_p (rxo_wr_wait_p),
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.rxo_wr_wait_n (rxo_wr_wait_n),
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.rxo_rd_wait_p (rxo_rd_wait_p),
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.rxo_rd_wait_n (rxo_rd_wait_n),
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.txo_lclk_p (txo_lclk_p),
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.txo_lclk_n (txo_lclk_n),
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.txo_frame_p (txo_frame_p),
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.txo_frame_n (txo_frame_n),
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.txo_data_p (txo_data_p[7:0]),
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.txo_data_n (txo_data_n[7:0]),
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.chipid (chipid[11:0]),
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.cclk_p (cclk_p),
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.cclk_n (cclk_n),
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.chip_nreset (chip_nreset),
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.mailbox_not_empty (mailbox_not_empty),
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.mailbox_full (mailbox_full),
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.timeout (timeout),
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.rxwr_access (rxwr_access),
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.rxwr_packet (rxwr_packet[PW-1:0]),
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.rxrd_access (rxrd_access),
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.rxrd_packet (rxrd_packet[PW-1:0]),
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.rxrr_access (rxrr_access),
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.rxrr_packet (rxrr_packet[PW-1:0]),
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.txwr_wait (txwr_wait),
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.txrd_wait (txrd_wait),
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.txrr_wait (txrr_wait),
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// Inputs
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.sys_nreset (sys_nreset),
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.sys_clk (sys_clk),
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.rxi_lclk_p (rxi_lclk_p),
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.rxi_lclk_n (rxi_lclk_n),
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.rxi_frame_p (rxi_frame_p),
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.rxi_frame_n (rxi_frame_n),
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.rxi_data_p (rxi_data_p[7:0]),
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.rxi_data_n (rxi_data_n[7:0]),
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.txi_wr_wait_p (txi_wr_wait_p),
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.txi_wr_wait_n (txi_wr_wait_n),
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.txi_rd_wait_p (txi_rd_wait_p),
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.txi_rd_wait_n (txi_rd_wait_n),
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.rxwr_wait (rxwr_wait),
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.rxrd_wait (rxrd_wait),
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.rxrr_wait (rxrr_wait),
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.txwr_access (txwr_access),
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.txwr_packet (txwr_packet[PW-1:0]),
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.txrd_access (txrd_access),
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.txrd_packet (txrd_packet[PW-1:0]),
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.txrr_access (txrr_access),
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.txrr_packet (txrr_packet[PW-1:0]));
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//########################################################
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//AXI SLAVE
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//########################################################
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defparam esaxi.S_IDW=S_IDW;
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defparam esaxi.ID=ID;
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esaxi esaxi (.s_axi_aclk (sys_clk),
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/*AUTOINST*/
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// Outputs
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.txwr_access (txwr_access),
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.txwr_packet (txwr_packet[PW-1:0]),
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.txrd_access (txrd_access),
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.txrd_packet (txrd_packet[PW-1:0]),
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.rxrr_wait (rxrr_wait),
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.s_axi_arready (s_axi_arready),
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.s_axi_awready (s_axi_awready),
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.s_axi_bid (s_axi_bid[S_IDW-1:0]),
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.s_axi_bresp (s_axi_bresp[1:0]),
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.s_axi_bvalid (s_axi_bvalid),
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.s_axi_rid (s_axi_rid[S_IDW-1:0]),
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.s_axi_rdata (s_axi_rdata[31:0]),
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.s_axi_rlast (s_axi_rlast),
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.s_axi_rresp (s_axi_rresp[1:0]),
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.s_axi_rvalid (s_axi_rvalid),
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.s_axi_wready (s_axi_wready),
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// Inputs
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.txwr_wait (txwr_wait),
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.txrd_wait (txrd_wait),
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.rxrr_access (rxrr_access),
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.rxrr_packet (rxrr_packet[PW-1:0]),
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.s_axi_aresetn (s_axi_aresetn),
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.s_axi_arid (s_axi_arid[S_IDW-1:0]),
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.s_axi_araddr (s_axi_araddr[31:0]),
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.s_axi_arburst (s_axi_arburst[1:0]),
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.s_axi_arcache (s_axi_arcache[3:0]),
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.s_axi_arlock (s_axi_arlock),
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.s_axi_arlen (s_axi_arlen[7:0]),
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.s_axi_arprot (s_axi_arprot[2:0]),
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.s_axi_arqos (s_axi_arqos[3:0]),
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.s_axi_arsize (s_axi_arsize[2:0]),
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.s_axi_arvalid (s_axi_arvalid),
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.s_axi_awid (s_axi_awid[S_IDW-1:0]),
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.s_axi_awaddr (s_axi_awaddr[31:0]),
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.s_axi_awburst (s_axi_awburst[1:0]),
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.s_axi_awcache (s_axi_awcache[3:0]),
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.s_axi_awlock (s_axi_awlock),
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.s_axi_awlen (s_axi_awlen[7:0]),
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.s_axi_awprot (s_axi_awprot[2:0]),
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.s_axi_awqos (s_axi_awqos[3:0]),
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.s_axi_awsize (s_axi_awsize[2:0]),
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.s_axi_awvalid (s_axi_awvalid),
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.s_axi_bready (s_axi_bready),
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.s_axi_rready (s_axi_rready),
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.s_axi_wid (s_axi_wid[S_IDW-1:0]),
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.s_axi_wdata (s_axi_wdata[31:0]),
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.s_axi_wlast (s_axi_wlast),
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.s_axi_wstrb (s_axi_wstrb[3:0]),
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.s_axi_wvalid (s_axi_wvalid));
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//########################################################
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//AXI MASTER INTERFACE
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//########################################################
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defparam emaxi.M_IDW=M_IDW;
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emaxi emaxi (.m_axi_aclk (sys_clk),
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/*AUTOINST*/
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// Outputs
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.rxwr_wait (rxwr_wait),
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.rxrd_wait (rxrd_wait),
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.txrr_access (txrr_access),
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.txrr_packet (txrr_packet[PW-1:0]),
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.m_axi_awid (m_axi_awid[M_IDW-1:0]),
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.m_axi_awaddr (m_axi_awaddr[31:0]),
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.m_axi_awlen (m_axi_awlen[7:0]),
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.m_axi_awsize (m_axi_awsize[2:0]),
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.m_axi_awburst (m_axi_awburst[1:0]),
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.m_axi_awlock (m_axi_awlock),
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.m_axi_awcache (m_axi_awcache[3:0]),
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.m_axi_awprot (m_axi_awprot[2:0]),
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.m_axi_awqos (m_axi_awqos[3:0]),
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.m_axi_awvalid (m_axi_awvalid),
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.m_axi_wid (m_axi_wid[M_IDW-1:0]),
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.m_axi_wdata (m_axi_wdata[63:0]),
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.m_axi_wstrb (m_axi_wstrb[7:0]),
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.m_axi_wlast (m_axi_wlast),
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.m_axi_wvalid (m_axi_wvalid),
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.m_axi_bready (m_axi_bready),
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.m_axi_arid (m_axi_arid[M_IDW-1:0]),
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.m_axi_araddr (m_axi_araddr[31:0]),
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.m_axi_arlen (m_axi_arlen[7:0]),
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.m_axi_arsize (m_axi_arsize[2:0]),
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.m_axi_arburst (m_axi_arburst[1:0]),
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.m_axi_arlock (m_axi_arlock),
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.m_axi_arcache (m_axi_arcache[3:0]),
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.m_axi_arprot (m_axi_arprot[2:0]),
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.m_axi_arqos (m_axi_arqos[3:0]),
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.m_axi_arvalid (m_axi_arvalid),
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.m_axi_rready (m_axi_rready),
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// Inputs
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.rxwr_access (rxwr_access),
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.rxwr_packet (rxwr_packet[PW-1:0]),
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.rxrd_access (rxrd_access),
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.rxrd_packet (rxrd_packet[PW-1:0]),
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.txrr_wait (txrr_wait),
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.m_axi_aresetn (m_axi_aresetn),
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.m_axi_awready (m_axi_awready),
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.m_axi_wready (m_axi_wready),
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.m_axi_bid (m_axi_bid[M_IDW-1:0]),
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.m_axi_bresp (m_axi_bresp[1:0]),
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.m_axi_bvalid (m_axi_bvalid),
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|
.m_axi_arready (m_axi_arready),
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.m_axi_rid (m_axi_rid[M_IDW-1:0]),
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.m_axi_rdata (m_axi_rdata[63:0]),
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.m_axi_rresp (m_axi_rresp[1:0]),
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.m_axi_rlast (m_axi_rlast),
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.m_axi_rvalid (m_axi_rvalid));
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endmodule // elink
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// Local Variables:
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// verilog-library-directories:("." "../../erx/hdl" "../../etx/hdl" "../../memory/hdl")
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// End:
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