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3fa5fce86f
- Making default parameter generic (will need to fix elink next..) - Brining out fifo status for cdc module, goes to status registers (very useful for debugging)
82 lines
2.4 KiB
Verilog
82 lines
2.4 KiB
Verilog
//########################################################################
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//# FIFO based clock Domain Crosser
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//########################################################################
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module oh_fifo_cdc (/*AUTOARG*/
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// Outputs
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wait_out, access_out, packet_out, prog_full, full, empty,
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// Inputs
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nreset, clk_in, access_in, packet_in, clk_out, wait_in
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);
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//#####################################################################
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//# INTERFACE
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//#####################################################################
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parameter DW = 104; // FIFO width
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parameter DEPTH = 32; // FIFO depth (entries)
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parameter TARGET = "GENERIC"; // GENERIC,XILINX,ALTERA,GENERIC,ASIC
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parameter WAIT = 0; // assert random prog_full wait
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//shared async reset
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input nreset;
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//input packet
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input clk_in;
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input access_in;
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input [DW-1:0] packet_in;
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output wait_out;
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//output packet
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input clk_out;
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output access_out;
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output [DW-1:0] packet_out;
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input wait_in;
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//status
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output prog_full;
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output full;
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output empty;
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//#####################################################################
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//# BODY
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//#####################################################################
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//Local wires
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wire wr_en;
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wire rd_en;
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wire empty;
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wire full;
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wire prog_full;
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reg access_out;
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//We use the prog_full clean out any buffers in pipe
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//Assumption: The "full" state should never be reached!
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assign wr_en = access_in;
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assign rd_en = ~empty & ~wait_in;
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assign wait_out = prog_full;
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//Holds access high while waiting
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always @ (posedge clk_out or negedge nreset)
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if(!nreset)
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access_out <= 1'b0;
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else if(~wait_in)
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access_out <= rd_en;
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//Read response fifo (from master)
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oh_fifo_async #(.TARGET(TARGET),
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.DW(DW),
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.DEPTH(DEPTH),
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.WAIT(WAIT))
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fifo (.prog_full (prog_full),
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.full (full),
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.rd_count (),
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.nreset (nreset),
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.dout (packet_out[DW-1:0]),
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.empty (empty),
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.wr_clk (clk_in),
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.rd_clk (clk_out),
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.wr_en (wr_en),
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.din (packet_in[DW-1:0]),
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.rd_en (rd_en)
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);
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endmodule // fifo_cdc
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