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29 lines
497 B
Verilog
29 lines
497 B
Verilog
module oh_mux3(/*AUTOARG*/
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// Outputs
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out,
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// Inputs
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in0, in1, in2, sel0, sel1, sel2
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);
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parameter DW=1;
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//data inputs
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input [DW-1:0] in0;
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input [DW-1:0] in1;
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input [DW-1:0] in2;
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//select inputs
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input sel0;
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input sel1;
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input sel2;
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output [DW-1:0] out;
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assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] |
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{(DW){sel1}} & in1[DW-1:0] |
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{(DW){sel2}} & in2[DW-1:0]);
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endmodule // oh_mux3
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