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93330039e0
-First bug was a typo. Cursing AXI for making every signal look exactly the same at first glance. Not good use practice -Second bug was sloppy. (removed pipeline stage on write data by mistake)
574 lines
19 KiB
Verilog
574 lines
19 KiB
Verilog
module esaxi (/*autoarg*/
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// Outputs
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emwr_access, emwr_write, emwr_datamode, emwr_ctrlmode,
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emwr_dstaddr, emwr_data, emwr_srcaddr, emrq_access, emrq_write,
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emrq_datamode, emrq_ctrlmode, emrq_dstaddr, emrq_data,
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emrq_srcaddr, emrr_rd_en, mi_clk, mi_rx_emmu_sel, mi_tx_emmu_sel,
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mi_ecfg_sel, mi_embox_sel, mi_we, mi_addr, mi_din, s_axi_arready,
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s_axi_awready, s_axi_bresp, s_axi_bvalid, s_axi_rdata, s_axi_rlast,
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s_axi_rresp, s_axi_rvalid, s_axi_wready,
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// Inputs
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emwr_progfull, emrq_progfull, emrr_data, emrr_access, mi_ecfg_dout,
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mi_tx_emmu_dout, mi_rx_emmu_dout, mi_embox_dout, ecfg_tx_ctrlmode,
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ecfg_coreid, ecfg_timeout_enable, s_axi_aclk, s_axi_aresetn,
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s_axi_araddr, s_axi_arburst, s_axi_arcache, s_axi_arlen,
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s_axi_arprot, s_axi_arqos, s_axi_arsize, s_axi_arvalid,
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s_axi_awaddr, s_axi_awburst, s_axi_awcache, s_axi_awlen,
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s_axi_awprot, s_axi_awqos, s_axi_awsize, s_axi_awvalid,
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s_axi_bready, s_axi_rready, s_axi_wdata, s_axi_wlast, s_axi_wstrb,
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s_axi_wvalid
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);
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parameter [11:0] c_read_tag_addr = 12'h810;//emesh srcaddr tag
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parameter integer c_s_axi_addr_width = 30; //address width
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parameter [11:0] ELINKID = 12'h810;
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/*****************************/
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/*Write request for TX fifo */
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/*****************************/
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output emwr_access;
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output emwr_write;
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output [1:0] emwr_datamode;
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output [3:0] emwr_ctrlmode;
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output [31:0] emwr_dstaddr;
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output [31:0] emwr_data;
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output [31:0] emwr_srcaddr;
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input emwr_progfull;
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/*****************************/
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/*Read request for TX fifo */
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/*****************************/
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output emrq_access;
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output emrq_write;
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output [1:0] emrq_datamode;
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output [3:0] emrq_ctrlmode;
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output [31:0] emrq_dstaddr;
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output [31:0] emrq_data;
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output [31:0] emrq_srcaddr;
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input emrq_progfull; //TODO? used for?
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/*****************************/
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/*Read response from RX fifo */
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/*****************************/
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//Only data needed
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input [31:0] emrr_data;
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input emrr_access;
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output emrr_rd_en; //update read fifo
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/*****************************/
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/*Register RD/WR Interface */
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/*****************************/
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output mi_clk;
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output mi_rx_emmu_sel;
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output mi_tx_emmu_sel;
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output mi_ecfg_sel;
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output mi_embox_sel;
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output mi_we;
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output [19:0] mi_addr;
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output [31:0] mi_din;
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input [31:0] mi_ecfg_dout;
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input [31:0] mi_tx_emmu_dout;
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input [31:0] mi_rx_emmu_dout;
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input [31:0] mi_embox_dout;
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/*****************************/
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/*Config Settings */
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/*****************************/
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input [3:0] ecfg_tx_ctrlmode;
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input [11:0] ecfg_coreid;
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input ecfg_timeout_enable;
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/*****************************/
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/*AXI slave interface */
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/*****************************/
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//Clock and reset
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input s_axi_aclk;
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input s_axi_aresetn;
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//Read address channel
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input [29:0] s_axi_araddr;
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input [1:0] s_axi_arburst;
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input [3:0] s_axi_arcache;
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input [7:0] s_axi_arlen;
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input [2:0] s_axi_arprot;
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input [3:0] s_axi_arqos;
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output s_axi_arready;
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input [2:0] s_axi_arsize;
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input s_axi_arvalid;
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//Write address channel
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input [29:0] s_axi_awaddr;
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input [1:0] s_axi_awburst;
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input [3:0] s_axi_awcache;
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input [7:0] s_axi_awlen;
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input [2:0] s_axi_awprot;
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input [3:0] s_axi_awqos;
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output s_axi_awready;
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input [2:0] s_axi_awsize;
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input s_axi_awvalid;
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//Buffered write response channel
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input s_axi_bready;
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output [1:0] s_axi_bresp;
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output s_axi_bvalid;
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//Read channel
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output [31:0] s_axi_rdata;
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output s_axi_rlast;
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input s_axi_rready;
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output [1:0] s_axi_rresp;
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output s_axi_rvalid;
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//Write channel
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input [31:0] s_axi_wdata;
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input s_axi_wlast;
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output s_axi_wready;
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input [3:0] s_axi_wstrb;
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input s_axi_wvalid;
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// axi4full signals
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reg s_axi_awready;
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reg s_axi_wready;
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reg s_axi_bvalid;
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reg [1:0] s_axi_bresp;
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reg s_axi_arready;
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reg [31:0] emwr_data_reg;
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reg [31:0] emwr_dstaddr_reg;
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reg [3:0] emwr_ctrlmode_reg;
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reg [1:0] emwr_datamode_reg;
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reg [31:0] axi_awaddr; // 32b for epiphany addr
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reg [1:0] axi_awburst;
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reg [2:0] axi_awsize;
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reg [31:0] axi_araddr;
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reg [7:0] axi_arlen;
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reg [1:0] axi_arburst;
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reg [2:0] axi_arsize;
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reg [31:0] s_axi_rdata;
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reg [1:0] s_axi_rresp;
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reg s_axi_rlast;
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reg s_axi_rvalid;
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reg read_active;
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reg [31:0] read_addr;
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reg write_active;
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reg b_wait; // waiting to issue write response (unlikely?)
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reg emwr_access;
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reg [3:0] emwr_ctrlmode;
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reg [1:0] emwr_datamode;
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reg [31:0] emwr_dstaddr;
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reg [31:0] emwr_data;
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reg [31:0] emwr_srcaddr; //upper 32 bits in case 64 bit writes are supported
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reg emrq_access;
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reg [3:0] emrq_ctrlmode;
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reg [1:0] emrq_datamode;
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reg [31:0] emrq_dstaddr;
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reg [31:0] emrq_srcaddr; //upper 32 bits in case 64 bit writes are supported
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reg pre_wr_en; // delay for data alignment
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reg ractive_reg; // need leading edge of active for 1st req
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reg rnext;
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reg mi_rx_emmu_reg;
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reg mi_tx_emmu_reg;
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reg mi_ecfg_reg;
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reg mi_embox_reg;
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reg mi_rd_reg;
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wire last_wr_beat;
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wire last_rd_beat;
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wire mi_wr;
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wire mi_rd;
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wire mi_we;
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wire mi_en;
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wire [31:0] mi_dout;
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wire mi_sel;
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wire [31:0] emrr_mux_data;
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//local parameter for addressing 32 bit / 64 bit c_s_axi_data_width
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//addr_lsb is used for addressing 32/64 bit registers/memories
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//addr_lsb = 2 for 32 bits (n downto 2)
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//addr_lsb = 3 for 64 bits (n downto 3)
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//TODO? Do we really need this?
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localparam integer addr_lsb = 2;
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//###################################################
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//#WRITE ADDRESS CHANNEL
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//###################################################
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assign last_wr_beat = s_axi_wready & s_axi_wvalid & s_axi_wlast;
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// axi_awready is asserted when there is no write transfer in progress
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always @(posedge s_axi_aclk )
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begin
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if(~s_axi_aresetn)
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begin
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s_axi_awready <= 1'b0;
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write_active <= 1'b0;
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end
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else
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begin
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// we're always ready for an address cycle if we're not doing something else
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// note: might make this faster by going ready on last beat instead of after,
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// but if we want the very best each channel should be fifo'd.
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if( ~s_axi_awready & ~write_active & ~b_wait )
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s_axi_awready <= 1'b1;
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else if( s_axi_awvalid )
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s_axi_awready <= 1'b0;
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// the write cycle is "active" as soon as we capture an address, it
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// ends on the last beat.
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if( s_axi_awready & s_axi_awvalid )
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write_active <= 1'b1;
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else if( last_wr_beat )
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write_active <= 1'b0;
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end // else: !if(~s_axi_aresetn)
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end // always @ (posedge s_axi_aclk )
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// capture address & other aw info, update address during cycle
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always @( posedge s_axi_aclk )
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if (~s_axi_aresetn)
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begin
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//s_axi_bid <= 'd0; // capture for write response
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axi_awaddr[31:0] <= 32'd0;
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axi_awsize[2:0] <= 3'd0;
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axi_awburst[1:0] <= 2'd0;
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end
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else
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begin
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if( s_axi_awready & s_axi_awvalid )
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begin
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//TODO: If we support only one host read, why the need?
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//s_axi_bid <= s_axi_awid;
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//TODO: something is wrong here!!!
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axi_awaddr[31:0] <= { ecfg_coreid[11:c_s_axi_addr_width-20],
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s_axi_awaddr[29:0] };
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axi_awsize <= s_axi_awsize; // 0=byte, 1=16b, 2=32b
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axi_awburst <= s_axi_awburst; // type, 0=fixed, 1=incr, 2=wrap
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end
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else if( s_axi_wvalid & s_axi_wready )
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if( axi_awburst == 2'b01 )
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begin //incremental burst
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// the write address for all the beats in the transaction are increments by the data width.
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// note: this should be based on awsize instead to support narrow bursts, i think.
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//TODO: BUG!!
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axi_awaddr[31:addr_lsb] <= axi_awaddr[31:addr_lsb] + 30'd1;
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//awaddr alignedto data width
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axi_awaddr[addr_lsb-1:0] <= {addr_lsb{1'b0}};
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end // both fixed & wrapping types are treated as fixed, no update.
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end // else: !if(~s_axi_aresetn)
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//###################################################
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//#WRITE CHANNEL
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//###################################################
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always @ (posedge s_axi_aclk)
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if(~s_axi_aresetn)
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s_axi_wready <= 1'b0;
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else
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begin
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if( last_wr_beat )
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s_axi_wready <= 1'b0;
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else if( write_active )
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s_axi_wready <= ~emwr_progfull;
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end
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// implement write response logic generation
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// the write response and response valid signals are asserted by the slave
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// at the end of each transaction, burst or single.
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always @( posedge s_axi_aclk )
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if (~s_axi_aresetn)
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begin
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s_axi_bvalid <= 1'b0;
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s_axi_bresp[1:0] <= 2'b0;
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b_wait <= 1'b0;
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end
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else
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begin
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if( last_wr_beat )
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begin
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s_axi_bvalid <= 1'b1;
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s_axi_bresp[1:0] <= 2'b0; // 'okay' response
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b_wait <= ~s_axi_bready; // note: assumes bready will not drop without valid?
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end
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else if (s_axi_bready & s_axi_bvalid)
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begin
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s_axi_bvalid <= 1'b0;
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b_wait <= 1'b0;
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end
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end // else: !if( s_axi_aresetn == 1'b0 )
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//###################################################
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//#READ REQUEST CHANNEL
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//###################################################
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assign last_rd_beat = s_axi_rvalid & s_axi_rlast & s_axi_rready;
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always @( posedge s_axi_aclk )
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if (~s_axi_aresetn)
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begin
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s_axi_arready <= 1'b0;
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read_active <= 1'b0;
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end
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else
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begin
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//arready
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if( ~s_axi_arready & ~read_active )
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s_axi_arready <= 1'b1;
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else if( s_axi_arvalid )
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s_axi_arready <= 1'b0;
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//read_active
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if( s_axi_arready & s_axi_arvalid )
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read_active <= 1'b1;
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else if( last_rd_beat )
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read_active <= 1'b0;
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end // else: !if( s_axi_aresetn == 1'b0 )
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//Read address channel state machine
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always @( posedge s_axi_aclk )
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if (~s_axi_aresetn)
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begin
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axi_araddr[31:0] <= 0;
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axi_arlen <= 8'd0;
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axi_arburst <= 2'd0;
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axi_arsize[2:0] <= 3'b0;
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s_axi_rlast <= 1'b0;
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//s_axi_rid <= 'd0;
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end
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else
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begin
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if( s_axi_arready & s_axi_arvalid )
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begin
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//TODO: something is wrong..
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axi_araddr[31:0] <= { ecfg_coreid[11:c_s_axi_addr_width-20],
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s_axi_araddr[29:0] }; // start address of transfer
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axi_arlen <= s_axi_arlen;
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axi_arburst <= s_axi_arburst;
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axi_arsize <= s_axi_arsize;
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s_axi_rlast <= ~(|s_axi_arlen);
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//s_axi_rid <= s_axi_arid;
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end
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else if( s_axi_rvalid & s_axi_rready)
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begin
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axi_arlen <= axi_arlen - 1;
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if(axi_arlen == 8'd1)
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s_axi_rlast <= 1'b1;
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if( s_axi_arburst == 2'b01)
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begin //incremental burst
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// the read address for all the beats in the transaction are increments by awsize
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// note: this should be based on awsize instead to support narrow bursts, i think?
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axi_araddr[c_s_axi_addr_width - 1:addr_lsb] <= axi_araddr[c_s_axi_addr_width - 1:addr_lsb] + 1;
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//araddr aligned to 4 byte boundary
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axi_araddr[addr_lsb-1:0] <= {addr_lsb{1'b0}};
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//for awsize = 4 bytes (010)
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end
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end // if ( s_axi_rvalid & s_axi_rready)
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end // else: !if( s_axi_aresetn == 1'b0 )
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//###################################################
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//#WRITE DATA
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//###################################################
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assign emwr_write = 1'b1;
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always @( posedge s_axi_aclk )
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if (~s_axi_aresetn)
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begin
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emwr_data_reg[31:0] <= 32'd0;
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emwr_dstaddr_reg[31:0] <= 32'd0;
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emwr_ctrlmode_reg[3:0] <= 4'd0;
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emwr_datamode_reg[1:0] <= 2'd0;
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emwr_access <= 1'b0;
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pre_wr_en <= 1'b0;
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end
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else
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begin
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pre_wr_en <= s_axi_wready & s_axi_wvalid;
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emwr_access <= pre_wr_en;
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emwr_ctrlmode_reg[3:0] <= ecfg_tx_ctrlmode[3:0];//static
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emwr_datamode_reg[1:0] <= axi_awsize[1:0];
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emwr_dstaddr_reg[31:2] <= axi_awaddr[31:2]; //set lsbs of address based on write strobes
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casez(s_axi_wstrb[3:0])
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4'b???1://aligned
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begin
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emwr_data_reg[31:0] <= s_axi_wdata[31:0];
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emwr_dstaddr_reg[1:0] <= 2'd0;
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end
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4'b??10 : //shift by byte
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begin
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emwr_data_reg[31:0] <= {8'd0, s_axi_wdata[31:8]};
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emwr_dstaddr_reg[1:0] <= 2'd1;
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end
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4'b?100 : //shift by two bytes
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begin
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emwr_data_reg[31:0] <= {16'd0, s_axi_wdata[31:16]};
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emwr_dstaddr_reg[1:0] <= 2'd2;
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end
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default: //shift by three bytes
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begin
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emwr_data_reg[31:0] <= {24'd0, s_axi_wdata[31:24]};
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emwr_dstaddr_reg[1:0] <= 2'd3;
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end
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endcase // casez (s_axi_wstrb[3:0])
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end // else: !if(~s_axi_aresetn)
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//Pipeline stage
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always @( posedge s_axi_aclk )
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if (~s_axi_aresetn)
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begin
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emwr_srcaddr[31:0] <= 32'd0;
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emwr_data[31:0] <= 32'd0;
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emwr_dstaddr[31:0] <= 32'd0;
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emwr_ctrlmode[3:0] <= 4'd0;
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emwr_datamode[1:0] <= 2'd0;
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emwr_access <= 1'b0;
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end
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else
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begin
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emwr_srcaddr[31:0] <= 32'b0;
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emwr_data[31:0] <= emwr_data_reg[31:0];
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emwr_dstaddr[31:0] <= emwr_dstaddr_reg[31:0];
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emwr_ctrlmode[3:0] <= emwr_ctrlmode_reg[3:0];
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emwr_datamode[1:0] <= emwr_datamode_reg[1:0];
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end // else: !if(~s_axi_aresetn)
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//###################################################
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//#READ REQUEST (DATA CHANNEL)
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//###################################################
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// ------------------------------------------
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// -- read data handler
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// -- reads are performed by sending a read
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// -- request out the tx port and waiting for
|
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// -- data to come back through the rx port.
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// --
|
|
// -- because elink reads are not generally
|
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// -- returned in order, we will only allow
|
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// -- one at a time. that's ok because reads
|
|
// -- are to be avoided for speed anyway.
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// ------------------------------------------
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|
|
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// since we're only sending one req at a time we can ignore the fifo flags
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// always read response data immediately
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assign emrr_rd_en = emrr_access & ~mi_rd_reg; //TODO: Verify this assumption!!!
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|
|
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assign emrq_write = 1'b0;
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assign emrq_data[31:0] = 32'b0;
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|
|
|
always @( posedge s_axi_aclk )
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if (~s_axi_aresetn)
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|
begin
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emrq_access <= 1'b0;
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emrq_datamode[1:0] <= 2'd0;
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emrq_ctrlmode[3:0] <= 4'd0;
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emrq_dstaddr[31:0] <= 32'd0;
|
|
emrq_srcaddr[31:0] <= 32'd0;
|
|
ractive_reg <= 1'b0;
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|
rnext <= 1'b0;
|
|
end
|
|
else
|
|
begin
|
|
ractive_reg <= read_active; //read request state machone
|
|
rnext <= s_axi_rvalid & s_axi_rready & ~s_axi_rlast;
|
|
emrq_access <= ( ~ractive_reg & read_active ) | rnext;
|
|
emrq_datamode[1:0] <= axi_arsize[1:0];
|
|
emrq_ctrlmode[3:0] <= ecfg_tx_ctrlmode;
|
|
emrq_dstaddr[31:0] <= axi_araddr[31:0];
|
|
emrq_srcaddr[31:0] <= {c_read_tag_addr[11:0], 20'd0};//TODO? What can we do with lower 32 bits?
|
|
end
|
|
|
|
|
|
//Read response AXI state machine
|
|
always @( posedge s_axi_aclk )
|
|
if ( s_axi_aresetn == 1'b0 )
|
|
begin
|
|
s_axi_rvalid <= 1'b0;
|
|
s_axi_rdata[31:0] <= 32'd0;
|
|
s_axi_rresp <= 2'd0;
|
|
end
|
|
else
|
|
begin
|
|
if( emrr_access | mi_rd_reg )
|
|
begin
|
|
s_axi_rvalid <= 1'b1;
|
|
s_axi_rresp <= 2'd0;
|
|
case( axi_arsize[1:0] )
|
|
2'b00: s_axi_rdata[31:0] <= {4{emrr_mux_data[7:0]}}; //8-bit
|
|
2'b01: s_axi_rdata[31:0] <= {2{emrr_mux_data[15:0]}}; //16-bit
|
|
default: s_axi_rdata[31:0] <= emrr_mux_data[31:0]; //32-bit
|
|
endcase // case ( axi_arsize[1:0] )
|
|
end
|
|
else if( s_axi_rready )
|
|
s_axi_rvalid <= 1'b0;
|
|
end // else: !if( s_axi_aresetn == 1'b0 )
|
|
|
|
|
|
|
|
//###################################################
|
|
//#Register Inteface Logic
|
|
//###################################################
|
|
|
|
|
|
assign mi_clk = s_axi_aclk;
|
|
|
|
//Register file access (from slave)
|
|
assign mi_wr = emwr_access & (emwr_dstaddr[31:20]==ELINKID);
|
|
assign mi_rd = emrq_access & (emrq_dstaddr[31:20]==ELINKID);
|
|
|
|
//Only 32 bit writes supported
|
|
assign mi_we = mi_wr;
|
|
assign mi_en = mi_wr | mi_rd;
|
|
|
|
//Read/write address
|
|
assign mi_addr[19:0] = mi_we ? emwr_dstaddr[19:0] :
|
|
emrq_dstaddr[19:0];
|
|
|
|
//Block select
|
|
assign mi_ecfg_sel = mi_en & (mi_addr[19:16]==`EGROUP_MMR);
|
|
assign mi_rx_emmu_sel = mi_en & (mi_addr[19:16]==`EGROUP_RXMMU);
|
|
assign mi_tx_emmu_sel = mi_en & (mi_addr[19:16]==`EGROUP_TXMMU);
|
|
assign mi_embox_sel = mi_en & (mi_addr[19:16]==`EGROUP_EMBOX);
|
|
|
|
//Data
|
|
assign mi_din[31:0] = emwr_data[31:0];
|
|
|
|
//Readback
|
|
always@ (posedge mi_clk)
|
|
begin
|
|
mi_ecfg_reg <= mi_ecfg_sel;
|
|
mi_rx_emmu_reg <= mi_rx_emmu_sel;
|
|
mi_tx_emmu_reg <= mi_tx_emmu_sel;
|
|
mi_embox_reg <= mi_embox_sel;
|
|
mi_rd_reg <= mi_rd;
|
|
end
|
|
|
|
//Data mux
|
|
assign mi_dout[31:0] = mi_ecfg_reg ? mi_ecfg_dout[31:0] :
|
|
mi_rx_emmu_reg ? mi_rx_emmu_dout[31:0] :
|
|
mi_tx_emmu_reg ? mi_tx_emmu_dout[31:0] :
|
|
mi_embox_dout[31:0];
|
|
/********************************/
|
|
/*INTERFACE TO AXI SLAVE */
|
|
/********************************/
|
|
|
|
//Read Response
|
|
assign emrr_mux_data[31:0] = mi_rd_reg ? mi_dout[31:0] :
|
|
emrr_data[31:0];
|
|
|
|
endmodule
|