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41 lines
1.3 KiB
Verilog
41 lines
1.3 KiB
Verilog
//#############################################################################
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//# Function: CRC combinatorial encoder wrapper #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_crc #( parameter TYPE = "ETH", // type: "ETH", "OTHER"
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parameter DW = 8) // width of data
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(
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input [DW-1:0] data_in, // input data
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input [CW-1:0] crc_state, // input crc state
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output [CW-1:0] crc_next // next crc state
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);
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localparam CW = 32; // width of polynomial
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generate
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if(TYPE=="ETH")
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begin
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if(DW==8)
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oh_crc32_8b crc(/*AUTOINST*/
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// Outputs
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.crc_next (crc_next[31:0]),
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// Inputs
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.data_in (data_in[7:0]),
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.crc_state (crc_state[31:0]));
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else if(DW==64)
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oh_crc32_64b crc(/*AUTOINST*/
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// Outputs
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.crc_next (crc_next[31:0]),
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// Inputs
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.data_in (data_in[63:0]),
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.crc_state (crc_state[31:0]));
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end // if (TYPE=="ETH")
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endgenerate
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endmodule // oh_crc
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