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553ee31400
Vivado does not pre-process defines in the module declaration. The result is that each module with this type of declaration is AutoDisabled by Vivado Moving the top level define to a localparam fixes this problem Signed-off-by: Peter Saunderson <peteasa@gmail.com>
37 lines
1.1 KiB
Verilog
37 lines
1.1 KiB
Verilog
//#############################################################################
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//# Function: Latch data when clk=0 #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_lat0 #(parameter DW = 1 // data width
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)
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( input clk, // clk, latch when clk=0
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input [DW-1:0] in, // input data
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output [DW-1:0] out // output data (stable/latched when clk=1)
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);
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localparam ASIC = `CFG_ASIC; // use ASIC lib
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generate
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if(ASIC)
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begin : g0
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asic_lat0 ilat [DW-1:0] (.clk(clk),
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.in(in[DW-1:0]),
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.out(out[DW-1:0]));
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end
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else
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begin : g0
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reg [DW-1:0] out_reg;
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always @ (clk or in)
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if (!clk)
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out_reg[DW-1:0] <= in[DW-1:0];
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assign out[DW-1:0] = out_reg[DW-1:0];
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end // else: !if(ASIC)
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endgenerate
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endmodule // oh_lat0
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