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87 lines
2.5 KiB
Verilog
87 lines
2.5 KiB
Verilog
module c2c (/*AUTOARG*/
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// Outputs
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tx_access, tx_packet, tx_clk, wait_out, rx_wait, access_out,
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packet_out,
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// Inputs
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clk, io_clk, nreset, divcfg, tx_wait, access_in, packet_in,
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datasize, rx_clk, rx_access, rx_packet, wait_in
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);
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//#####################################################################
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//# INTERFACE
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//#####################################################################
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//parameters
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parameter PW = `C2C_PW; // data width (core)
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parameter IOW = `C2C_IOW; // IO data width
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localparam CW = $clog2(2*PW/IOW);// transfer count width
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// reset, clk
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input clk; // main core clock
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input io_clk; // clock for TX
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input nreset; // async active low reset
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input [3:0] divcfg; // tx clock divider config
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////////////////
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// tx interface
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output tx_access; // access signal for IO
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output [IOW-1:0] tx_packet; // packet for IO
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output tx_clk; // clock for IO
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input tx_wait; // pushback from IO
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input access_in; // fifo data valid
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input [PW-1:0] packet_in; // fifo packet
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input [CW-1:0] datasize; // size of data transmitted
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output wait_out; // wait pushback for fifo
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////////////////
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// rx interface
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input rx_clk; // rx clock
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input rx_access; // rx access
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input [IOW-1:0] rx_packet; // rx packet
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output rx_wait; // pushback from IO
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output access_out; // fifo data valid
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output [PW-1:0] packet_out; // fifo packet
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input wait_in; // wait pushback for fifo
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/*AUTOOUTPUT*/
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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ctx #(.IOW(IOW),
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.PW(PW))
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ctx (/*AUTOINST*/
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// Outputs
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.wait_out (wait_out),
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.tx_clk (tx_clk),
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.tx_access (tx_access),
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.tx_packet (tx_packet[IOW-1:0]),
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// Inputs
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.clk (clk),
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.io_clk (io_clk),
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.nreset (nreset),
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.divcfg (divcfg[3:0]),
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.access_in (access_in),
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.packet_in (packet_in[PW-1:0]),
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.datasize (datasize[CW-1:0]),
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.tx_wait (tx_wait));
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crx #(.IOW(IOW),
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.PW(PW))
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crx (/*AUTOINST*/
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// Outputs
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.rx_wait (rx_wait),
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.access_out (access_out),
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.packet_out (packet_out[PW-1:0]),
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// Inputs
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.clk (clk),
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.nreset (nreset),
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.datasize (datasize[CW-1:0]),
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.rx_clk (rx_clk),
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.rx_access (rx_access),
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.rx_packet (rx_packet[IOW-1:0]),
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.wait_in (wait_in));
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endmodule // c2c
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