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90 lines
2.5 KiB
Verilog
90 lines
2.5 KiB
Verilog
//##########################################################################
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//#
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//# - DW is fixed per design
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//# - size of packet being fed should be programmable
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//# - data is transmitted LSB first!
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//#
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//#
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//##########################################################################
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module crx_protocol (/*AUTOARG*/
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// Outputs
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fifo_access, fifo_packet,
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// Inputs
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clk, nreset, datasize, io_access, io_packet
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);
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//#####################################################################
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//# INTERFACE
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//#####################################################################
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//parameters
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parameter PW = 104; // packet width (core)
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parameter IOW = 16; // io packet width
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localparam CW = $clog2(2*PW/IOW); // transfer count width
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//clock and reset
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input clk; // core clock
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input nreset; // async active low reset
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//config
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input [CW-1:0] datasize; // dynamic width of output data
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//16 bit interface
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input io_access; // access signal from IO
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input [2*IOW-1:0] io_packet; // data from IO
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//wide input interface
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output fifo_access; // access for fifo
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output [PW-1:0] fifo_packet; // packet for fifo
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//regs
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reg [2:0] crx_state;
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reg [CW-1:0] crx_count;
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reg [PW-1:0] fifo_packet;
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reg fifo_access;
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//##########################
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//# STATE MACHINE
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//##########################
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`define CRX_IDLE 3'b000
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`define CRX_BUSY 3'b001
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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crx_state[2:0] <= `CRX_IDLE;
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else
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case (crx_state[2:0])
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`CRX_IDLE: crx_state[2:0] <= io_access ? `CRX_BUSY : `CRX_IDLE;
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`CRX_BUSY: crx_state[2:0] <= transfer_done ? `CRX_IDLE : `CRX_BUSY;
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default: crx_state[2:0] <= 'b0;
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endcase // case (crx_state[2:0])
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//shift data
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always @ (posedge clk)
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if(crx_state[2:0]==`CRX_BUSY)
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crx_count[CW-1:0] <= crx_count[CW-1:0] - 1'b1;
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else
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crx_count[CW-1:0] <= datasize[CW-1:0];
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assign transfer_done = ~(|crx_count[CW-1:0]) & (crx_state[2:0]==`CRX_BUSY);
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//pipeline access signal
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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fifo_access <= 'b0;
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else
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fifo_access <= transfer_done;
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//create a wide parallel packet
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always @ (posedge clk)
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if ((crx_state[2:0]==`CRX_BUSY) & ~transfer_done)
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fifo_packet[PW-1:0] <= {fifo_packet[PW-2*IOW-1:0],io_packet[2*IOW-1:0]};
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endmodule // crx_protocol
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