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35 lines
1.4 KiB
Markdown
35 lines
1.4 KiB
Markdown
=======
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# OH!
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An Open Hardware Modle Library for Chip and FPGA Designers
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The library is written in vanilla Verilog. Pull requests accepted.
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| Spec | Status | Description |
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|---------------------|--------|---------------------------------------------|
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| [axi](axi) | | AXI network interface stuff |
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| [common](common) | | Common moini modules (syncrhonziers etc) |
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| [edma](edma) | | A bare metal DMA module |
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| [elink](elink) | | The Epiphany point to point LVDS link |
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| [emailbox](emailbox)| | A simple mailnox with interrupt output |
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| [emmu](emmu) | | A simple memory map translation unit |
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| [memory](memory) | | Various simple memory structures (RAM/FIFO) |
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| [emesh](emesh) | | Epiphany emesh packet related circuits |
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| [xilibs](xilibs) | | Simulation modules for Xilinx primitives |
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## Building
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```
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git clone https://github.com/parallella/oh.git
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cd oh
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mkdir build
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cd build
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../configure
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make elink
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```
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## License
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``
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This library is made available with a LGPL V3 copyleft license. By our interpretation, Verilog is software and chips/bitstreams are the hardware equivalent of a binary program. We will look into this issue further in the future, but in the meantime, please consider this a strict copyleft library.
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```
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