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6e93d0399a
-This needs to be resolved! Currently there is a simulation problem with the PLL and IDDR circuit, likely due to the clock divider. Amazingly enough the circuit works in sim and FPGA, but there was some redundant logic hiding this. -Need to take a closer look at this to get the non-blocking/blocking right in PLL and CLKDIV
This folder contains basic Xilinx verilog primitives
All primitives should be written in "synthesizable" code that can be simulated in Verilator and which should work correctly when synthesized.