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100 lines
2.9 KiB
Verilog
100 lines
2.9 KiB
Verilog
//WARNING: Pass through logic
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module emesh_if (/*AUTOARG*/
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// Outputs
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cmesh_wait_out, cmesh_access_out, cmesh_packet_out, rmesh_wait_out,
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rmesh_access_out, rmesh_packet_out, xmesh_wait_out,
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xmesh_access_out, xmesh_packet_out, emesh_wait_out,
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emesh_access_out, emesh_packet_out,
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// Inputs
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cmesh_access_in, cmesh_packet_in, cmesh_wait_in, rmesh_access_in,
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rmesh_packet_in, rmesh_wait_in, xmesh_access_in, xmesh_packet_in,
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xmesh_wait_in, emesh_access_in, emesh_packet_in, emesh_wait_in
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);
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parameter AW = 32;
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parameter PW = 2*AW+40;
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//##Cmesh##
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input cmesh_access_in;
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input [PW-1:0] cmesh_packet_in;
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output cmesh_wait_out;
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output cmesh_access_out;
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output [PW-1:0] cmesh_packet_out;
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input cmesh_wait_in;
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//##Rmesh##
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input rmesh_access_in;
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input [PW-1:0] rmesh_packet_in;
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output rmesh_wait_out;
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output rmesh_access_out;
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output [PW-1:0] rmesh_packet_out;
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input rmesh_wait_in;
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//##Xmesh##
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input xmesh_access_in;
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input [PW-1:0] xmesh_packet_in;
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output xmesh_wait_out;
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output xmesh_access_out;
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output [PW-1:0] xmesh_packet_out;
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input xmesh_wait_in;
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//##Emesh##
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input emesh_access_in;
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input [PW-1:0] emesh_packet_in;
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output emesh_wait_out;
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//core-->io
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output emesh_access_out;
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output [PW-1:0] emesh_packet_out;
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input emesh_wait_in;
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//#####################################################
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//# EMESH-->(RMESH/XMESH/CMESH)
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//#####################################################
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assign cmesh_access_out = emesh_access_in & emesh_packet_in[0];
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assign rmesh_access_out = emesh_access_in & ~emesh_packet_in[0];
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//Don't drive on xmesh for now
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assign xmesh_access_out = 1'b0;
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//Distribute emesh to xmesh,cmesh, rmesh
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assign cmesh_packet_out[PW-1:0] = emesh_packet_in[PW-1:0];
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assign rmesh_packet_out[PW-1:0] = emesh_packet_in[PW-1:0];
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assign xmesh_packet_out[PW-1:0] = emesh_packet_in[PW-1:0];
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assign emesh_wait_out = cmesh_wait_in |
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rmesh_wait_in |
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xmesh_wait_in;
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//#####################################################
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//# (RMESH/XMESH/CMESH)-->EMESH
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//#####################################################
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assign emesh_access_out = cmesh_access_in |
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rmesh_access_in |
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xmesh_access_in;
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//TODO: Make round robin?? (Fancify)
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assign emesh_packet_out[PW-1:0] = cmesh_access_in ? cmesh_packet_in[PW-1:0] :
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rmesh_access_in ? rmesh_packet_in[PW-1:0] :
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xmesh_packet_in[PW-1:0];
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assign cmesh_wait_out = (cmesh_access_in & emesh_wait_in);
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assign rmesh_wait_out = rmesh_access_in &
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(emesh_wait_in | cmesh_access_in);
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assign xmesh_wait_out = xmesh_access_in &
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(emesh_wait_in | cmesh_access_in | rmesh_access_in);
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endmodule // emesh_if
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