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91 lines
4.0 KiB
Tcl
91 lines
4.0 KiB
Tcl
###########################################################
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# DEFINITIONS
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###########################################################
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set design parallella
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set design axi_elink
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set root "../../.."
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set partname "xc7z020clg400-1"
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set archive [concat $design.zip]
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set report_dir ./reports
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set results_dir ./results
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#Make this a list (+foreach)
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set elink_ip_repo_dir ../../../elink/ip/xilinx
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###########################################################
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# CREATE PROJECT
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###########################################################
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create_project -force $design . -part $partname
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set_property target_language Verilog [current_project]
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###########################################################
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# Create Report/Results Directory
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###########################################################
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if ![file exists $report_dir] {file mkdir $report_dir}
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if ![file exists $results_dir] {file mkdir $results_dir}
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###########################################################
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# Add eLink IP to IP Repository
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###########################################################
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set ip_repo_paths [get_property ip_repo_paths [current_project]]
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set_property ip_repo_paths "$elink_ip_repo_dir $ip_repo_paths" [current_project]
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update_ip_catalog
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###########################################################
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# Create Block Design
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###########################################################
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create_bd_design "system"
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source ./parallella_elink_base_bd.tcl
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validate_bd_design
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###########################################################
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# Write BD TCL (FOR STORAGE)
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###########################################################
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write_bd_tcl -force ${results_dir}/parallella_elink_base_bd.tcl
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###########################################################
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# Create HDL Wrapper (??)
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###########################################################
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make_wrapper -files [get_files C:/Parallella/ipi_parallella_elink_base/project_ipi/project_ipi.srcs/sources_1/bd/parallella_bd/parallella_bd.bd] -top
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add_files -norecurse C:/Parallella/ipi_parallella_elink_base/project_ipi/project_ipi.srcs/sources_1/bd/parallella_bd/hdl/parallella_bd_wrapper.v
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add_files -fileset constrs_1 -norecurse C:/Parallella/ipi_parallella_elink_base/sources/parallella_io.xdc
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add_files -fileset constrs_1 -norecurse C:/Parallella/ipi_parallella_elink_base/sources/parallella_timing.xdc
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# [IP_Flow 19-3298] Detected external port differences while upgrading IP 'fifo_async_104x16'. These changes may impact your design.
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# [Synth 8-439] module 'erx_clocks' not found ["c:/Parallella/ipi_parallella_elink_base/project_ipi/project_ipi.srcs/sources_1/elink/hdl/erx.v":90]
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# [Synth 8-439] module 'etx_clocks' not found ["c:/Parallella/ipi_parallella_elink_base/project_ipi/project_ipi.srcs/sources_1/elink/hdl/etx.v":92]
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# -> Patched components.xml
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# [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified.
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# Please check your design and connect them if needed:
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# /axi_elink_0/s_axi_wid
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# [IP_Flow 19-3298] Detected external port differences while upgrading IP 'fifo_async_104x16'. These changes may impact your design.
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# [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified.
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# Please check your design and connect them if needed:
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# /axi_elink_0/s_axi_wid
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# [Designutils 20-1280] Could not find module 'fifo_async_104x16'. The XDC file c:/Parallella/ipi_parallella_elink_base/project_ipi/project_ipi.srcs/sources_1/xilibs/ip/fifo_async_104x16/fifo_async_104x16/fifo_async_104x16.xdc will not be read for any cell of this module.
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# [Designutils 20-1280] Could not find module 'fifo_async_104x16'. The XDC file c:/Parallella/ipi_parallella_elink_base/project_ipi/project_ipi.srcs/sources_1/xilibs/ip/fifo_async_104x16/fifo_async_104x16/fifo_async_104x16_clocks.xdc will not be read for any cell of this module.
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###########################################################
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# Implement Design
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###########################################################
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#launch_runs synth_1
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#wait_on_run synth_1
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#launch_runs impl_1
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#wait_on_run impl_1
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