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Andreas Olofsson bb084f1670 Adding skeleton for adi sdr design
Now need to integrate elink in this
2015-11-11 00:42:14 -05:00

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306 B
Tcl

#STEP1: DEFINE KEY PARAMETERS
source ./system_params.tcl
#STEP2: CREATE PROJECT AND READ IN FILES
source ../../../common/fpga/system_init.tcl
#STEP 3 (OPTIONAL): EDIT system.bd in VIVADO gui, then go to STEP 4.
##...
#STEP 4: SYNTEHSIZE AND CREATE BITSTRAM
source ../../../common/fpga/system_build.tcl