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OH! : Open Hardware for FPGA and ASIC designers

CONTENT

Module	Status	Description
accelerator	FPGA	Accelerator tutorial
chip	SILICON	Chip design reference flow
common	SILICON*	Library of generally useful components
emesh	SILICON	Emesh interface utility circuits
elink	SILICON	Point to point LVDS link
emailbox	FPGA	Mailbox with interrupt output
emmu	FPGA	Memory transaction translation unit
irqc	SILICON	Epiphany nested interrupt controller
xilibs	FPGA	Simulation modules for Xilinx primitives

NOTES:

• "SILICON": Silicon validated
• "FPGA": FPGA validated
• "SIM": Simulation only
• Common folder includes modules with mixed status. Some are silicon validated, others have only been simulated.

LICENSE

The OH! repository source code is licensed under the MIT license unless otherwise specified. See LICENSE for MIT copyright terms. Design specific licenses can be found in the folder root (eg: aes/LICENSE)

CONTRIBUTING

Instructions for contributing can be found HERE.

RECOMMEND TOOLS

• Verilator Simulator
• Emacs Verilog Mode
• Icarus Simulator
• GTKWave
• Verilog-Perl

RECOMMENDED READING

• Glossary
• Chip constants
• Verilog Reference

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