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58 lines
1.8 KiB
Verilog
58 lines
1.8 KiB
Verilog
/* verilator lint_off WIDTH */
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module emesh_monitor(/*AUTOARG*/
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// Inputs
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clk, reset, itrace, etime, emesh_access, emesh_packet, emesh_wait
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);
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parameter AW = 32;
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parameter DW = 32;
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parameter NAME = "cpu";
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parameter PW = 104;
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//BASIC INTERFACE
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input clk;
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input reset;
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input itrace;
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input [31:0] etime;
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//MESH TRANSCTION
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input emesh_access;
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input [PW-1:0] emesh_packet;
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input emesh_wait;
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//core name for trace
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reg [63:0] name=NAME;
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reg [31:0] ftrace;
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initial
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begin
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ftrace = $fopen({NAME,".trace"}, "w");
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end
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always @ (posedge clk)
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if(itrace & ~reset & emesh_access & ~emesh_wait)
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begin
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//$fwrite(ftrace, "TIME=%h\n",etime[31:0]);
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$fwrite(ftrace, "%h_%h_%h_%h\n",emesh_packet[103:72], emesh_packet[71:40],emesh_packet[39:8],
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{emesh_packet[7:4],emesh_packet[3:2],emesh_packet[1],emesh_access});
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end
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endmodule // emesh_monitor
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/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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