Andreas Olofsson a1722b7ae6 Adding timeout circuit

2015-04-27 16:02:15 -04:00

..

ecfg_base.v

Register name shuffle

2015-04-27 09:28:52 -04:00

ecfg_if.v

Register map change

2015-04-24 17:38:01 -04:00

ecfg_rx.v

Added read watchdog timer

2015-04-27 13:00:00 -04:00

ecfg_tx.v

Register name shuffle

2015-04-27 09:28:52 -04:00

ecfg.v

Message box working...

2015-04-19 21:55:07 -04:00

eclocks.v

Verilator based lint cleanup

2015-04-23 18:57:55 -04:00

elink_constants.v

Renaming constants file

2015-04-22 13:56:48 -04:00

elink_regmap.v

Register name shuffle

2015-04-27 09:28:52 -04:00

elink.v

Added "timeout" to elink interface

2015-04-27 15:11:56 -04:00

emaxi.v

Bug fix, missing pipeline stage on read response

2015-04-21 17:14:30 -04:00

ememory.v

Memory bug fix

2015-04-26 08:29:50 -04:00

ereset.v

Cleanup

2015-04-18 16:26:32 -04:00

erx_disty.v

Added "timeout" to elink interface

2015-04-27 15:11:56 -04:00

erx_io.v

Address remapping integration

2015-04-24 17:39:05 -04:00

erx_mux.v

Readback cleanup

2015-04-24 17:27:35 -04:00

erx_protocol.v

Address remapping integration

2015-04-24 17:39:05 -04:00

erx_remap.v

RX address remap bug fix

2015-04-27 09:29:22 -04:00

erx_timer.v

Adding timeout circuit

2015-04-27 16:02:15 -04:00

erx.v

Added "timeout" to elink interface

2015-04-27 15:11:56 -04:00

esaxi.v

File cleanup

2015-04-23 18:10:07 -04:00

etx_arbiter.v

Added read watchdog timer

2015-04-27 13:00:00 -04:00

etx_io.v

Address remapping integration

2015-04-24 17:39:05 -04:00

etx_mux.v

Readback cleanup

2015-04-24 17:27:35 -04:00

etx_protocol.v

Adding test mode registers for transmit path

2015-04-27 00:04:30 -04:00

etx_remap.v

Adding RX/TX address remapping

2015-04-24 17:29:05 -04:00

etx.v

Added read watchdog timer

2015-04-27 13:00:00 -04:00