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b25ad633f7
RX/TX interfaces should be mininmized and standalone Adding mux to consolidate to one "dout"
23 lines
412 B
Verilog
23 lines
412 B
Verilog
module etx_mux (/*AUTOARG*/
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// Outputs
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mi_dout,
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// Inputs
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mi_clk, mi_en, mi_addr, mi_tx_emmu_dout, mi_tx_cfg_dout
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);
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parameter AW = 32;
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parameter DW = 32;
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//Needed for selecting data
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input mi_clk;
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input mi_en;
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input [19:0] mi_addr;
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input [DW-1:0] mi_tx_emmu_dout;
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input [DW-1:0] mi_tx_cfg_dout;
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output [DW-1:0] mi_dout;
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endmodule // etx_mux
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