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41 lines
767 B
Verilog
41 lines
767 B
Verilog
module oh_mux4(/*AUTOARG*/
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// Outputs
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out,
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// Inputs
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in0, in1, in2, in3, sel0, sel1, sel2, sel3
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);
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parameter DW=99;
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//data inputs
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input [DW-1:0] in0;
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input [DW-1:0] in1;
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input [DW-1:0] in2;
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input [DW-1:0] in3;
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//select inputs
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input sel0;
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input sel1;
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input sel2;
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input sel3;
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output [DW-1:0] out;
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wire error;
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assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] |
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{(DW){sel1}} & in1[DW-1:0] |
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{(DW){sel2}} & in2[DW-1:0] |
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{(DW){sel3}} & in3[DW-1:0]);
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assign error = (sel0 | sel1 | sel2 | sel3) &
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~(sel0 ^ sel1 ^ sel2 ^ sel3);
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always @ (posedge error)
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$display ("ERROR at in oh_mux4 %m at ",$time);
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endmodule // oh_mux4
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