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f7806821c7
- using rx reset, safer as this stays in reset longer, until the clock has hade time to clean up the rest
219 lines
7.9 KiB
Verilog
219 lines
7.9 KiB
Verilog
module erx (/*AUTOARG*/
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// Outputs
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rx_active, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p,
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rxo_rd_wait_n, rxwr_access, rxwr_packet, rxrd_access, rxrd_packet,
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rxrr_access, rxrr_packet, erx_cfg_wait, rx_lclk_div4, erx_nreset,
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timeout, mailbox_full, mailbox_not_empty,
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// Inputs
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soft_reset, sys_nreset, sys_clk, tx_active, rxi_lclk_p, rxi_lclk_n,
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rxi_frame_p, rxi_frame_n, rxi_data_p, rxi_data_n, rxwr_wait,
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rxrd_wait, rxrr_wait, erx_cfg_access, erx_cfg_packet
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);
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parameter AW = 32;
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parameter DW = 32;
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parameter PW = 104;
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parameter RFAW = 6;
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parameter ID = 12'h800;
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parameter IOSTD_ELINK = "LVDS_25";
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parameter ETYPE = 1;
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//Synched resets, clock
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input soft_reset; // sw driven reset
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input sys_nreset; // async reset
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input sys_clk; // system clock for fifo/clocks
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input tx_active; // holds rx in check until tx has booted
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output rx_active; // indicates RX and TX are active
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//FROM IO Pins
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input rxi_lclk_p, rxi_lclk_n; // rx clock input
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input rxi_frame_p, rxi_frame_n; // rx frame signal
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input [7:0] rxi_data_p, rxi_data_n; // rx data
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output rxo_wr_wait_p,rxo_wr_wait_n; // rx write pushback output
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output rxo_rd_wait_p,rxo_rd_wait_n; // rx read pushback output
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//Master write
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output rxwr_access;
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output [PW-1:0] rxwr_packet;
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input rxwr_wait;
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//Master read request
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output rxrd_access;
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output [PW-1:0] rxrd_packet;
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input rxrd_wait;
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//Slave read response
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output rxrr_access;
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output [PW-1:0] rxrr_packet;
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input rxrr_wait;
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//Configuration Interface (from ETX)
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input erx_cfg_access;
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input [PW-1:0] erx_cfg_packet;
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output erx_cfg_wait;
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output rx_lclk_div4;
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output erx_nreset;
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//Readback timeout (synchronized to sys_c
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output timeout;
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output mailbox_full;
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output mailbox_not_empty;
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//hack up for now
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assign timeout = 1'b0;
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/*AUTOOUTPUT*/
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire erx_io_nreset; // From erx_clocks of erx_clocks.v
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wire [44:0] idelay_value; // From erx_core of erx_core.v
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wire load_taps; // From erx_core of erx_core.v
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wire rx_access; // From erx_io of erx_io.v
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wire rx_burst; // From erx_io of erx_io.v
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wire rx_clkin; // From erx_io of erx_io.v
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wire rx_lclk; // From erx_clocks of erx_clocks.v
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wire [PW-1:0] rx_packet; // From erx_io of erx_io.v
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wire rx_rd_wait; // From erx_core of erx_core.v
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wire rx_wr_wait; // From erx_core of erx_core.v
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wire rxrd_fifo_access; // From erx_core of erx_core.v
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wire [PW-1:0] rxrd_fifo_packet; // From erx_core of erx_core.v
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wire rxrd_fifo_wait; // From erx_fifo of erx_fifo.v
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wire rxrr_fifo_access; // From erx_core of erx_core.v
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wire [PW-1:0] rxrr_fifo_packet; // From erx_core of erx_core.v
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wire rxrr_fifo_wait; // From erx_fifo of erx_fifo.v
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wire rxwr_fifo_access; // From erx_core of erx_core.v
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wire [PW-1:0] rxwr_fifo_packet; // From erx_core of erx_core.v
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wire rxwr_fifo_wait; // From erx_fifo of erx_fifo.v
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// End of automatics
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/***********************************************************/
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/*CLOCK/RESET */
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/***********************************************************/
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erx_clocks erx_clocks(/*AUTOINST*/
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// Outputs
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.rx_lclk (rx_lclk),
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.rx_lclk_div4 (rx_lclk_div4),
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.rx_active (rx_active),
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.erx_nreset (erx_nreset),
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.erx_io_nreset (erx_io_nreset),
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// Inputs
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.sys_nreset (sys_nreset),
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.soft_reset (soft_reset),
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.tx_active (tx_active),
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.sys_clk (sys_clk),
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.rx_clkin (rx_clkin));
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/***********************************************************/
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/*RECEIVER I/O LOGIC */
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/***********************************************************/
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erx_io #(.ETYPE(ETYPE))
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erx_io (
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/*AUTOINST*/
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// Outputs
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.rx_clkin (rx_clkin),
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.rxo_wr_wait_p (rxo_wr_wait_p),
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.rxo_wr_wait_n (rxo_wr_wait_n),
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.rxo_rd_wait_p (rxo_rd_wait_p),
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.rxo_rd_wait_n (rxo_rd_wait_n),
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.rx_access (rx_access),
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.rx_burst (rx_burst),
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.rx_packet (rx_packet[PW-1:0]),
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// Inputs
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.erx_io_nreset (erx_io_nreset),
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.rx_lclk (rx_lclk),
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.rx_lclk_div4 (rx_lclk_div4),
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.idelay_value (idelay_value[44:0]),
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.load_taps (load_taps),
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.rxi_lclk_p (rxi_lclk_p),
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.rxi_lclk_n (rxi_lclk_n),
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.rxi_frame_p (rxi_frame_p),
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.rxi_frame_n (rxi_frame_n),
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.rxi_data_p (rxi_data_p[7:0]),
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.rxi_data_n (rxi_data_n[7:0]),
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.rx_wr_wait (rx_wr_wait),
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.rx_rd_wait (rx_rd_wait));
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/**************************************************************/
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/*ELINK CORE LOGIC */
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/**************************************************************/
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/*erx_core AUTO_TEMPLATE ( .rx_packet (rx_packet[PW-1:0]),
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.rx_access (rx_access),
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.erx_cfg_access (erx_cfg_access),
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.erx_cfg_packet (erx_cfg_packet[PW-1:0]),
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.erx_cfg_wait (erx_cfg_wait),
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.rx_rd_wait (rx_rd_wait),
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.rx_wr_wait (rx_wr_wait),
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.\(.*\)_packet (\1_fifo_packet[PW-1:0]),
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.\(.*\)_access (\1_fifo_access),
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.\(.*\)_wait (\1_fifo_wait),
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);
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*/
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defparam erx_core.ID=ID;
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erx_core erx_core ( .clk (rx_lclk_div4),
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.nreset (erx_nreset),
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/*AUTOINST*/
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// Outputs
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.rx_rd_wait (rx_rd_wait), // Templated
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.rx_wr_wait (rx_wr_wait), // Templated
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.idelay_value (idelay_value[44:0]),
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.load_taps (load_taps),
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.rxrd_access (rxrd_fifo_access), // Templated
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.rxrd_packet (rxrd_fifo_packet[PW-1:0]), // Templated
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.rxrr_access (rxrr_fifo_access), // Templated
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.rxrr_packet (rxrr_fifo_packet[PW-1:0]), // Templated
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.rxwr_access (rxwr_fifo_access), // Templated
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.rxwr_packet (rxwr_fifo_packet[PW-1:0]), // Templated
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.erx_cfg_wait (erx_cfg_wait), // Templated
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.mailbox_full (mailbox_full),
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.mailbox_not_empty(mailbox_not_empty),
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// Inputs
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.rx_packet (rx_packet[PW-1:0]), // Templated
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.rx_access (rx_access), // Templated
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.rx_burst (rx_burst),
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.rxrd_wait (rxrd_fifo_wait), // Templated
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.rxrr_wait (rxrr_fifo_wait), // Templated
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.rxwr_wait (rxwr_fifo_wait), // Templated
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.erx_cfg_access (erx_cfg_access), // Templated
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.erx_cfg_packet (erx_cfg_packet[PW-1:0])); // Templated
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/************************************************************/
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/*FIFOs */
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/************************************************************/
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erx_fifo erx_fifo (
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/*AUTOINST*/
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// Outputs
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.rxwr_access (rxwr_access),
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.rxwr_packet (rxwr_packet[PW-1:0]),
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.rxrd_access (rxrd_access),
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.rxrd_packet (rxrd_packet[PW-1:0]),
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.rxrr_access (rxrr_access),
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.rxrr_packet (rxrr_packet[PW-1:0]),
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.rxrd_fifo_wait (rxrd_fifo_wait),
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.rxrr_fifo_wait (rxrr_fifo_wait),
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.rxwr_fifo_wait (rxwr_fifo_wait),
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// Inputs
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.sys_clk (sys_clk),
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.rx_lclk_div4 (rx_lclk_div4),
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.erx_nreset (erx_nreset),
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.rxwr_wait (rxwr_wait),
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.rxrd_wait (rxrd_wait),
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.rxrr_wait (rxrr_wait),
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.rxrd_fifo_access(rxrd_fifo_access),
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.rxrd_fifo_packet(rxrd_fifo_packet[PW-1:0]),
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.rxrr_fifo_access(rxrr_fifo_access),
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.rxrr_fifo_packet(rxrr_fifo_packet[PW-1:0]),
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.rxwr_fifo_access(rxwr_fifo_access),
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.rxwr_fifo_packet(rxwr_fifo_packet[PW-1:0]));
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endmodule // erx
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// Local Variables:
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// verilog-library-directories:(".")
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// End:
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