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Andreas Olofsson a36875ac09 Adding basic emehs transaction generator 
-Replace with DMA...
2015-05-05 21:39:20 -04:00
common
Clocks on during reset
2015-05-03 23:21:10 -04:00
edma
Making dma quiet until implemented
2015-05-03 23:23:02 -04:00
elink
Adding emesh as basic building block
2015-05-05 21:38:41 -04:00
emailbox
MILESTONE: Read/write works back and forth
2015-05-04 17:13:51 -04:00
emesh/hdl
Adding basic emehs transaction generator
2015-05-05 21:39:20 -04:00
emmu
Separating rd/wr wait for pipeline stall
2015-05-04 17:09:23 -04:00
memory
Using async reste on fifo output access signal
2015-05-04 17:07:55 -04:00
xilibs
Both input and output models were wrong.
2015-05-04 22:35:55 -04:00
.gitignore
Adding register access from RX
2015-04-27 23:51:00 -04:00
CONTRIBUTING.md
Basic infrastructure
2015-04-21 21:36:37 -04:00
COPYING
Basic infrastructure
2015-04-21 21:36:37 -04:00
LICENSE
Initial commit
2015-04-21 21:16:42 -04:00
README.md
Massive commit sequence coming...
2015-04-23 17:48:12 -04:00

README.md

=======

OH!

Open Hardware (Pure and Simple)

(work in progress...)

Description
No description provided
Readme MIT 43 MiB
Languages
Verilog 81.1%
Tcl 10.7%
C 5.6%
Shell 0.8%
Python 0.6%
Other 1.2%