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Yes it's simple, but youl should never have to rewrite this code For larger arbiters, too much risk of making a mistake... Arbitration mistakes aver nasty to find and nasty to debug!
47 lines
1.4 KiB
Verilog
47 lines
1.4 KiB
Verilog
/* Simple combinatorial priority arbiter
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* (lowest position has highest priority)
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*
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*/
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module arbiter_priority(/*AUTOARG*/
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// Outputs
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grant, await,
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// Inputs
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request
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);
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parameter ARW=99;
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input [ARW-1:0] request; //request vector
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output [ARW-1:0] grant; //grant (one hot)
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output [ARW-1:0] await; //grant mask
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genvar j;
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assign await[0] = 1'b0;
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generate for (j=ARW-1; j>=1; j=j-1) begin : gen_arbiter
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assign await[j] = |request[j-1:0];
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end
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endgenerate
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//grant circuit
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assign grant[ARW-1:0] = request[ARW-1:0] & ~await[ARW-1:0];
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endmodule // arbiter_priority
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/*
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Copyright (C) 2015 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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