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oh/parallella/fpga/parallella_base/system_params.tcl
2015-11-13 16:21:53 -05:00

29 lines
615 B
Tcl

# NOTE: See UG1118 for more information
#########################################
# VARIABLES
#########################################
set design parallella_base
set projdir ./
set root "../../.."
set partname "xc7z020clg400-1"
set hdl_files [list \
$root/common/hdl \
$root/memory/hdl \
$root/emesh/hdl \
$root/emmu/hdl \
$root/emailbox/hdl \
$root/edma/hdl \
$root/elink/hdl \
$root/parallella/hdl \
$root/parallella/hdl/parallella_base.v \
]
set ip_files [list \
$root/xilibs/ip/fifo_async_104x32.xci \
]
set constraints_files []