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98 lines
2.7 KiB
Verilog
98 lines
2.7 KiB
Verilog
module dut(/*AUTOARG*/
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// Outputs
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dut_active, wait_out, access_out, packet_out,
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// Inputs
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clk, nreset, vdd, vss, access_in, packet_in, wait_in
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);
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parameter AW = 32;
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parameter DW = 32;
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parameter CW = 2;
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parameter IDW = 12;
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parameter M_IDW = 6;
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parameter S_IDW = 12;
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parameter PW = 104;
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parameter N = 1;
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parameter ID = 12'h810;
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//#######################################
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//# CLOCK AND RESET
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//#######################################
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input clk;
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input nreset;
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input [N*N-1:0] vdd;
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input vss;
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output dut_active;
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//#######################################
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//#EMESH INTERFACE
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//#######################################
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//Stimulus Driven Transaction
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input [N-1:0] access_in;
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input [N*PW-1:0] packet_in;
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output [N-1:0] wait_out;
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//DUT driven transactoin
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output [N-1:0] access_out;
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output [N*PW-1:0] packet_out;
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input [N-1:0] wait_in;
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//TODO: finish readback
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wire [DW-1:0] mi_dout;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [3:0] mi_ctrlmode; // From e2p of packet2emesh.v
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wire [DW-1:0] mi_data; // From e2p of packet2emesh.v
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wire [1:0] mi_datamode; // From e2p of packet2emesh.v
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wire [AW-1:0] mi_dstaddr; // From e2p of packet2emesh.v
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wire [AW-1:0] mi_srcaddr; // From e2p of packet2emesh.v
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wire mi_write; // From e2p of packet2emesh.v
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// End of automatics
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assign dut_active = 1'b1;
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assign access_out = 'b0;
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assign wait_out = 'b0;
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assign packet_out[PW-1:0] = 'b0;
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/*packet2emesh AUTO_TEMPLATE (//Stimulus
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.\(.*\)_out(mi_\1[]),
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);
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*/
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//CONFIG INTERFACE
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packet2emesh e2p (/*AUTOINST*/
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// Outputs
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.write_out (mi_write), // Templated
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.datamode_out (mi_datamode[1:0]), // Templated
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.ctrlmode_out (mi_ctrlmode[3:0]), // Templated
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.data_out (mi_data[DW-1:0]), // Templated
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.dstaddr_out (mi_dstaddr[AW-1:0]), // Templated
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.srcaddr_out (mi_srcaddr[AW-1:0]), // Templated
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// Inputs
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.packet_in (packet_in[PW-1:0]));
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//TRACE
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etrace #(.ID(ID))
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etrace ( // Outputs
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.mi_dout (mi_dout[DW-1:0]),
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// Inputs
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.mi_en (access_in),
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.mi_we (mi_write),
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.mi_addr (mi_dstaddr[AW-1:0]),
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.mi_clk (clk),
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.mi_din (mi_data[DW-1:0]),
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.trace_clk (clk),
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.trace_trigger (1'b1),
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.trace_vector (mi_srcaddr[AW-1:0]),
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.nreset (nreset));
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endmodule // dv_elink
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// Local Variables:
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// verilog-library-directories:("." "../hdl" "../../emesh/dv" "../../emesh/hdl")
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// End:
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