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71 lines
2.1 KiB
Verilog
71 lines
2.1 KiB
Verilog
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/*###########################################################################
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# Function: Single port memory wrapper
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# To run without hardware platform dependancy use:
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# `define TARGET_CLEAN"
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############################################################################
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*/
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module memory_sp(/*AUTOARG*/
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// Outputs
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dout,
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// Inputs
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clk, en, wen, addr, din
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);
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parameter AW = 14;
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parameter DW = 32;
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parameter WED = DW/8; //one write enable per byte
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parameter MD = 1<<AW;//memory depth
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//write-port
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input clk; //clock
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input en; //memory access
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input [WED-1:0] wen; //write enable vector
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input [AW-1:0] addr;//address
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input [DW-1:0] din; //data input
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output [DW-1:0] dout;//data output
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reg [DW-1:0] ram [MD-1:0];
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reg [DW-1:0] rd_data;
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reg [DW-1:0] dout;
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//read port
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always @ (posedge clk)
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if(en)
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dout[DW-1:0] <= ram[addr[AW-1:0]];
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//write port
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generate
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genvar i;
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for (i = 0; i < WED; i = i+1) begin: gen_ram
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always @(posedge clk)
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begin
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if (wen[i] & en)
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ram[addr[AW-1:0]][(i+1)*8-1:i*8] <= din[(i+1)*8-1:i*8];
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end
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end
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endgenerate
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endmodule // memory_dp
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/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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