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a68bba1572
- Removed the cfgif block, too confusing. There is a good lesson here. Probably the n'th time I that I have been overzealous about reuse. When you end up adding a parameter to a block that duplicates the logic 2X it's always better to create two separate blocks... - Changed the register access interface to packet format - Change the priority on the etx_arbiter to pick read responses first - Removed redundant signals - Took away the read resonse bypass on remap in tx for now.. - Removed defparams (convention) - Unified wait signal on tx - Fixed cfg wait -
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OH!
An Open Hardware Library for Chip and FPGA designers written in Verilog
CONTENT
| Spec | Description |
|---|---|
| common | Common utility HW modules and scripts |
| edma | DMA module |
| emesh | Epiphany emesh related circuits |
| elink | Epiphany point to point LVDS link |
| emailbox | Simple mailbox with interrupt output |
| emmu | Simple memory transaction translation unit |
| etrace | Simple logic analyzer |
| memory | Various simple memory structures (RAM/FIFO) |
| xilibs | Simulation modules for Xilinx primitives |
LICENSE
The OH! repository source code is licensed under the MIT license unless otherwise specified. See LICENSE for full copyright terms.
CONTRIBUTING
Instructions for contributing can be found HERE.