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oh/verilog/faq.md
2015-10-14 23:11:07 -04:00

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## How to create a "hello world" in verilog?
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## How to run a simulation?
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## How to write a testbench?
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## How to create a synchronous flip-flop?
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## How to create an asynchronous flip-flop?
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## How to synchronize a reset across clock domains?
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## How to pass parameters at run time?
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## How to parametrize a module?
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## How to dump a waveform?
```
initial
begin
$dumpfile("test.vcd"); //file name to dump into
$dumpvars(0, top); //dump top level module
#10000
$finish; //end simulation
end
```
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## How to create a memory?
```
```
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## How to initialize a memory from a file?
```
initial
begin
end
```
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## How to view a waveform?
```
sudo apt-get install gtkwave
gtkwave test.vcd
```
-----------------------------------------
## How to reduce typing in emacs?
[Use verilog mode](Use verilog mode)
-----------------------------------------
## What are the most important emacs mode keywords?
* /*AUTOARG*/
* /*AUTOINST*/
* /*AUTOWIRE*/
* /*AUTOINPUT*/
* /*AUTOOUTPUT*/
* /*AUTOTEMPLATE*/