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92 lines
2.5 KiB
Verilog
92 lines
2.5 KiB
Verilog
module oh_fifo_sync (/*AUTOARG*/
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// Outputs
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dout, full, prog_full, empty, rd_count,
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// Inputs
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clk, nreset, din, wr_en, rd_en
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);
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//#####################################################################
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//# INTERFACE
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//#####################################################################
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parameter DEPTH = 4;
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parameter DW = 104;
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parameter PROG_FULL = DEPTH/2;
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parameter AW = $clog2(DEPTH);
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//clk/reset
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input clk; // clock
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input nreset; // active high async reset
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//write port
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input [DW-1:0] din; // data to write
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input wr_en; // write fifo
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//read port
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input rd_en; // read fifo
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output [DW-1:0] dout; // output data (next cycle)
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//Status
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output full; // fifo full
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output prog_full; // fifo is almost full
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output empty; // fifo is empty
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output [AW-1:0] rd_count; // valid entries in fifo
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//#####################################################################
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//# BODY
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//#####################################################################
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reg [AW-1:0] wr_addr;
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reg [AW-1:0] rd_addr;
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reg [AW-1:0] rd_count;
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assign empty = (rd_count[AW-1:0] == 0);
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assign prog_full = (rd_count[AW-1:0] >= PROG_FULL);
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assign full = (rd_count[AW-1:0] == DEPTH);
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always @ ( posedge clk or negedge nreset)
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if(!nreset)
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begin
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wr_addr[AW-1:0] <= 'd0;
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rd_addr[AW-1:0] <= 'b0;
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rd_count[AW-1:0] <= 'b0;
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end
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else if(wr_en & rd_en)
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begin
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wr_addr[AW-1:0] <= wr_addr[AW-1:0] + 'd1;
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rd_addr[AW-1:0] <= rd_addr[AW-1:0] + 'd1;
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end
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else if(wr_en)
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begin
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wr_addr[AW-1:0] <= wr_addr[AW-1:0] + 'd1;
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rd_count[AW-1:0]<= rd_count[AW-1:0] + 'd1;
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end
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else if(rd_en)
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begin
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rd_addr[AW-1:0] <= rd_addr[AW-1:0] + 'd1;
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rd_count[AW-1:0]<= rd_count[AW-1:0] - 'd1;
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end
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// GENERIC DUAL PORTED MEMORY
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oh_memory_dp
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#(.DW(DW),
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.AW(AW))
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mem (
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// read port
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.rd_dout (dout[DW-1:0]),
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.rd_clk (clk),
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.rd_en (rd_en),
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.rd_addr (rd_addr[AW-1:0]),
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// write port
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.wr_clk (clk),
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.wr_en (wr_en),
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.wr_wem ({(DW){1'b1}}),
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.wr_addr (wr_addr[AW-1:0]),
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.wr_din (din[DW-1:0])
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);
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endmodule // fifo_sync
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// Local Variables:
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// verilog-library-directories:(".")
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// End:
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