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38 lines
931 B
Verilog
38 lines
931 B
Verilog
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//convert serial stream to parallel
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module oh_ser2par (/*AUTOARG*/
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// Inputs
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clk, din, dout
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);
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//###############################################################
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//# Interface
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//###############################################################
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input clk; //sampling clock
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input din; //serial data
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output [DW-1:0] dout; //parallel data
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parameter DW = 64; //width of converter
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parameter TYPE = "MSB"; //MSB first or LSB first
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//###############################################################
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//# BODY
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//###############################################################
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reg [DW-1:0] dout;
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generate
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if(TYPE=="MSB")
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begin
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always @ (posedge clk)
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dout[DW-1:0] = {dout[DW-2:0],din};
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end
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else
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begin
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always @ (posedge clk)
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dout[DW-1:0] = {din,dout[DW-1:1]};
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end
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endgenerate
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endmodule // oh_ser2par
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