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44 lines
1.6 KiB
Markdown
44 lines
1.6 KiB
Markdown
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# OH!
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An Open Hardware library for Chip and FPGA designers written in Verilog.
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## CONTENT
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| Module | Description |
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|----------------------------|---------------------------------------------|
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| [accelerator](accelerator) | A simple accelerator tutorial |
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| [common](common) | Library of generally useful components |
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| [emesh](emesh) | Emesh interface utility circuits |
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| [elink](elink) | Point to point LVDS link |
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| [emailbox](emailbox) | Simple mailbox with interrupt output |
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| [emmu](emmu) | Simple memory transaction translation unit |
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| [xilibs](xilibs) | Simulation modules for Xilinx primitives |
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## LICENSE
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The OH! repository source code is licensed under the MIT license unless otherwise specified. See [LICENSE](LICENSE) for MIT copyright terms. Design specific licenses can be found in the folder root (eg: aes/LICENSE)
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## CONTRIBUTING
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Instructions for contributing can be found [HERE](CONTRIBUTING.md).
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## RECOMMEND TOOLS
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* [Verilator Simulator](http://www.veripool.org/wiki/verilator)
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* [Emacs Verilog Mode](http://www.veripool.org/wiki/verilog-mode)
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* [Icarus Simulator](http://iverilog.icarus.com)
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* [GTKWave](http://gtkwave.sourceforge.net)
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* [Verilog-Perl](http://www.veripool.org/wiki/verilog-perl)
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## RECOMMENDED READING
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* [Verilog Quick Reference](verilog/verilog_reference.md)
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* [Sunburst Design Verilog Papers](http://www.sunburst-design.com/papers)
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* [Sutherland Verilog Papers](http://www.sutherland-hdl.com/papers.html)
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