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59 lines
1.2 KiB
Verilog
59 lines
1.2 KiB
Verilog
module IDELAYE2_FINEDELAY (
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CNTVALUEOUT,
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DATAOUT,
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C,
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CE,
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CINVCTRL,
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CNTVALUEIN,
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DATAIN,
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IDATAIN,
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IFDLY,
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INC,
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LD,
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LDPIPEEN,
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REGRST
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);
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parameter CINVCTRL_SEL = "FALSE";
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parameter DELAY_SRC = "IDATAIN";
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parameter FINEDELAY = "BYPASS";
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parameter HIGH_PERFORMANCE_MODE = "FALSE";
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parameter IDELAY_TYPE = "FIXED";
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parameter integer IDELAY_VALUE = 0;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_DATAIN_INVERTED = 1'b0;
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parameter [0:0] IS_IDATAIN_INVERTED = 1'b0;
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parameter PIPE_SEL = "FALSE";
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parameter real REFCLK_FREQUENCY = 200.0;
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parameter SIGNAL_PATTERN = "DATA";
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`ifdef XIL_TIMING
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parameter LOC = "UNPLACED";
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parameter integer SIM_DELAY_D = 0;
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localparam DELAY_D = (IDELAY_TYPE == "VARIABLE") ? SIM_DELAY_D : 0;
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`endif // ifdef XIL_TIMING
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`ifndef XIL_TIMING
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integer DELAY_D=0;
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`endif // ifndef XIL_TIMING
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output [4:0] CNTVALUEOUT;
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output DATAOUT;
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input C;
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input CE;
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input CINVCTRL;
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input [4:0] CNTVALUEIN;
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input DATAIN;
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input IDATAIN;
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input [2:0] IFDLY;
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input INC;
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input LD;
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input LDPIPEEN;
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input REGRST;
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endmodule // IDELAYE2_FINEDELAY
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