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19fa611bb9
- adding more chip code - pushing memory stuff into common - making common "oh_" naming class -
41 lines
694 B
Verilog
41 lines
694 B
Verilog
/*
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* This module stretches a pulse by DW+1 clock cycles
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* Can be useful for synchronous clock transfers from fast to slow.
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* The block has one cycle latency
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*
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* in
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* clk
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* out
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*
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*/
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module oh_stretcher (/*AUTOARG*/
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// Outputs
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out,
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// Inputs
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clk, in, nrst
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);
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parameter CYCLES = 4;
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input clk;
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input in;
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input nrst;
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output out;
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reg [CYCLES-1:0] valid;
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always @ (posedge clk)
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if(!nrst)
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valid[CYCLES-1:0] <='b0;
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else if(in)
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valid[CYCLES-1:0] <={(CYCLES){1'b1}};
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else
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valid[CYCLES-1:0] <={valid[CYCLES-2:0],1'b0};
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assign out = valid[CYCLES-1];
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endmodule // oh_stretcher
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