Andreas Olofsson ac90486cb1 New MIO interface ...

- Work in progress, compiles but not yet debugged

2016-08-25 11:57:28 -04:00

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accelerator

Reorg! Why?

2016-03-22 08:13:40 -04:00

aes

Reorg! Why?

2016-03-22 08:13:40 -04:00

axi

AXI: emaxi: added nreset to instantiation of oh_dsync

2016-08-17 15:57:25 +01:00

chip

Fixing readme

2016-04-15 22:38:06 -04:00

common

Fixing non-blocking bug in dv

2016-08-25 11:45:20 -04:00

edma

Updating dma with new packet format

2016-05-15 15:49:39 -04:00

elink

TARGET changed back to XILINX from GENERIC

2016-08-17 15:30:38 +01:00

emailbox

TARGET changed back to XILINX from GENERIC

2016-08-17 15:30:38 +01:00

emesh

Updating to new emesh packet mappers

2016-05-15 15:46:49 -04:00

emmu

Using DEPTH as specifier for memory

2016-04-14 10:29:49 -04:00

etrace

Synthesis cleanup

2016-06-19 17:12:24 -04:00

gpio

Fefactoring to clarify register usage

2016-08-25 11:44:30 -04:00

mio

New MIO interface

2016-08-25 11:57:28 -04:00

parallella

Apply CFG_ASIC at the top level

2016-08-17 14:22:04 +01:00

pic

Cleaning up PIC code

2016-05-15 15:31:42 -04:00

risc-v

Reorg! Why?

2016-03-22 08:13:40 -04:00

spi

SPI code cleanup

2016-08-25 09:02:14 -04:00

xilibs

Moving xilibs/hdl to xilibs/dv

2016-06-19 17:18:44 -04:00