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oh/common/dv
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Andreas.Olofsson 89f995c20c Fixed nasty testbench problem that snuck in 
-The pass fail indicator is always tricky to get right
-In this case diff/done went high on the same cycle so everything was passing..
-Added check for same cyle completion/fail
-Also, changed the top level anme to "testbench", seems more popular
2020-08-19 19:34:03 -04:00
..
tests
Changing hierarchy to promote blocks
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cfg_random.v
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dut_clockdiv.v
Changing hierarchy to promote blocks
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dut_debouncer.v
Changing hierarchy to promote blocks
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dut_fifo_generic.v
Changing hierarchy to promote blocks
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dut_gray.v
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dut_template.v
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dv_driver.v
Changing hierarchy to promote blocks
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dv_random.v
Changing hierarchy to promote blocks
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dv_stimulus.v
Adding basic tesbench for stimulus function
2020-02-03 13:19:21 -05:00
dv_top.v
Changing hierarchy to promote blocks
2020-01-28 18:12:57 -05:00
firmware_example.hex
Adding firmware example for readmemh
2020-02-03 13:16:37 -05:00
libs.cmd
Adding include directorys to lib.cmd
2020-02-01 09:07:47 -05:00
oh_simchecker.v
Changing simchecker to hex.
2020-08-17 16:09:32 -04:00
oh_simctrl.v
Fixed nasty testbench problem that snuck in
2020-08-19 19:34:03 -04:00
oh.gtkw
Changing hierarchy to promote blocks
2020-01-28 18:12:57 -05:00
README.md
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run.sh
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2020-01-28 18:12:57 -05:00
stimulus.v
Making stimulus configurable
2020-02-06 12:50:34 -05:00
timescale.v
Changing hierarchy to promote blocks
2020-01-28 18:12:57 -05:00

README.md

What defines are used

iverilog -g2005 -DTARGET_SIM=1 $cfg $core.v $DV -f $LIBS -o $core.bin

How to compile all duts?

The script "build_all.sh" builds all dut files in this directory with random

./build_all.sh