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- Creating an arbitrary 'src' directory really doesn't help much... - Goal is to make each folder self contained - Make meta repos and individual repos have the same directory structure
62 lines
1.7 KiB
Verilog
62 lines
1.7 KiB
Verilog
module IDDR (/*AUTOARG*/
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// Outputs
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Q1, Q2,
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// Inputs
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C, CE, D, R, S
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);
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//Default parameters
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parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
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parameter INIT_Q1 = 1'b0;
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parameter INIT_Q2 = 1'b0;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter SRTYPE = "SYNC";
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localparam HOLDHACK = 0.1;
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output Q1; // IDDR registered output (first)
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output Q2; // IDDR registered output (second)
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input C; // clock
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input CE; // clock enable, set to high to clock in data
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input D; // data input from IOB
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input R; // sync or async reset
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input S; // syn/async "set to 1"
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//trick for string comparison
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localparam [152:1] DDR_CLK_EDGE_REG = DDR_CLK_EDGE;
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reg Q1_pos;
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reg Q1_reg;
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reg Q2_pos;
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reg Q2_neg;
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always @ (posedge C)
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if(CE)
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Q1_pos <= #(HOLDHACK) D;
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always @ (posedge C)
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if(CE)
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Q1_reg <= #(HOLDHACK) Q1_pos;
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always @ (negedge C)
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if(CE)
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Q2_neg <= #(HOLDHACK) D;
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always @ (posedge C)
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if(CE)
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Q2_pos <= #(HOLDHACK) Q2_neg;
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//Select behavior based on parameters
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assign Q1 = (DDR_CLK_EDGE_REG == "SAME_EDGE_PIPELINED") ? Q1_reg :
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(DDR_CLK_EDGE_REG == "SAME_EDGE") ? Q1_pos :
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1'b0;
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assign Q2 = (DDR_CLK_EDGE_REG == "SAME_EDGE_PIPELINED") ? Q2_pos :
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(DDR_CLK_EDGE_REG == "SAME_EDGE") ? Q2_pos :
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1'b0;
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endmodule // IDDR
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