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289024fd89
- Creating an arbitrary 'src' directory really doesn't help much... - Goal is to make each folder self contained - Make meta repos and individual repos have the same directory structure
114 lines
4.3 KiB
Verilog
114 lines
4.3 KiB
Verilog
module testbench();
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parameter NO_GPIO = 8;
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parameter SO_GPIO = 8;
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parameter EA_GPIO = 8;
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parameter WE_GPIO = 8;
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parameter NO_DOMAINS = 2;
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parameter SO_DOMAINS = 2;
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parameter EA_DOMAINS = 2;
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parameter WE_DOMAINS = 2;
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// Beginning of automatic inputs (from unused autoinst inputs)
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wire [EA_GPIO*8-1:0] ea_cfg; // To i0 of oh_padring.v
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wire [EA_GPIO-2:0] ea_dout; // To i0 of oh_padring.v
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wire [EA_GPIO-1:0] ea_ie; // To i0 of oh_padring.v
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wire [EA_GPIO-1:0] ea_oen; // To i0 of oh_padring.v
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wire [NO_GPIO*8-1:0] no_cfg; // To i0 of oh_padring.v
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wire [NO_GPIO-2:0] no_dout; // To i0 of oh_padring.v
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wire [NO_GPIO-1:0] no_ie; // To i0 of oh_padring.v
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wire [NO_GPIO-1:0] no_oen; // To i0 of oh_padring.v
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wire [SO_GPIO*8-1:0] so_cfg; // To i0 of oh_padring.v
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wire [SO_GPIO-2:0] so_dout; // To i0 of oh_padring.v
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wire [SO_GPIO-1:0] so_ie; // To i0 of oh_padring.v
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wire [SO_GPIO-1:0] so_oen; // To i0 of oh_padring.v
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wire [WE_GPIO*8-1:0] we_cfg; // To i0 of oh_padring.v
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wire [WE_GPIO-2:0] we_dout; // To i0 of oh_padring.v
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wire [WE_GPIO-1:0] we_ie; // To i0 of oh_padring.v
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wire [WE_GPIO-1:0] we_oen; // To i0 of oh_padring.v
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// End of automatics
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [EA_GPIO-1:0] ea_din; // From i0 of oh_padring.v
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wire [EA_GPIO-1:0] ea_pad; // To/From i0 of oh_padring.v
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wire [EA_DOMAINS-1:0] ea_vddio; // To/From i0 of oh_padring.v
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wire [EA_DOMAINS-1:0] ea_vssio; // To/From i0 of oh_padring.v
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wire [NO_GPIO-1:0] no_din; // From i0 of oh_padring.v
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wire [NO_GPIO-1:0] no_pad; // To/From i0 of oh_padring.v
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wire [NO_DOMAINS-1:0] no_vddio; // To/From i0 of oh_padring.v
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wire [NO_DOMAINS-1:0] no_vssio; // To/From i0 of oh_padring.v
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wire [SO_GPIO-1:0] so_din; // From i0 of oh_padring.v
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wire [SO_GPIO-1:0] so_pad; // To/From i0 of oh_padring.v
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wire [SO_DOMAINS-1:0] so_vddio; // To/From i0 of oh_padring.v
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wire [SO_DOMAINS-1:0] so_vssio; // To/From i0 of oh_padring.v
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wire vdd; // To/From i0 of oh_padring.v
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wire vss; // To/From i0 of oh_padring.v
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wire [WE_GPIO-1:0] we_din; // From i0 of oh_padring.v
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wire [WE_GPIO-1:0] we_pad; // To/From i0 of oh_padring.v
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wire [WE_DOMAINS-1:0] we_vddio; // To/From i0 of oh_padring.v
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wire [WE_DOMAINS-1:0] we_vssio; // To/From i0 of oh_padring.v
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// End of automatics
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oh_padring #(.TYPE("SOFT"),
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.NO_DOMAINS(NO_DOMAINS),
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.NO_GPIO(NO_GPIO),
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.SO_DOMAINS(SO_DOMAINS),
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.SO_GPIO(SO_GPIO),
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.EA_DOMAINS(EA_DOMAINS),
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.EA_GPIO(EA_GPIO),
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.WE_DOMAINS(WE_DOMAINS),
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.WE_GPIO(WE_GPIO))
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i0 (/*AUTOINST*/
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// Outputs
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.no_din (no_din[NO_GPIO-1:0]),
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.so_din (so_din[SO_GPIO-1:0]),
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.ea_din (ea_din[EA_GPIO-1:0]),
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.we_din (we_din[WE_GPIO-1:0]),
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// Inouts
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.vss (vss),
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.vdd (vdd),
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.no_vddio (no_vddio[NO_DOMAINS-1:0]),
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.no_vssio (no_vssio[NO_DOMAINS-1:0]),
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.no_pad (no_pad[NO_GPIO-1:0]),
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.so_vddio (so_vddio[SO_DOMAINS-1:0]),
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.so_vssio (so_vssio[SO_DOMAINS-1:0]),
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.so_pad (so_pad[SO_GPIO-1:0]),
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.ea_vddio (ea_vddio[EA_DOMAINS-1:0]),
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.ea_vssio (ea_vssio[EA_DOMAINS-1:0]),
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.ea_pad (ea_pad[EA_GPIO-1:0]),
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.we_vddio (we_vddio[WE_DOMAINS-1:0]),
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.we_vssio (we_vssio[WE_DOMAINS-1:0]),
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.we_pad (we_pad[WE_GPIO-1:0]),
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// Inputs
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.no_dout (no_dout[NO_GPIO-1-1:0]),
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.no_cfg (no_cfg[NO_GPIO*8-1:0]),
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.no_ie (no_ie[NO_GPIO-1:0]),
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.no_oen (no_oen[NO_GPIO-1:0]),
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.so_dout (so_dout[SO_GPIO-1-1:0]),
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.so_cfg (so_cfg[SO_GPIO*8-1:0]),
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.so_ie (so_ie[SO_GPIO-1:0]),
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.so_oen (so_oen[SO_GPIO-1:0]),
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.ea_dout (ea_dout[EA_GPIO-1-1:0]),
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.ea_cfg (ea_cfg[EA_GPIO*8-1:0]),
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.ea_ie (ea_ie[EA_GPIO-1:0]),
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.ea_oen (ea_oen[EA_GPIO-1:0]),
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.we_dout (we_dout[WE_GPIO-1-1:0]),
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.we_cfg (we_cfg[WE_GPIO*8-1:0]),
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.we_ie (we_ie[WE_GPIO-1:0]),
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.we_oen (we_oen[WE_GPIO-1:0]));
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initial
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begin
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$dumpvars;
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#1000 $finish;
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end
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endmodule // top
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// Local Variables:
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// verilog-library-directories:("." "../hdl")
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// End:
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