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101 lines
2.0 KiB
Verilog
101 lines
2.0 KiB
Verilog
module elink_monitor(/*AUTOARG*/
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// Inputs
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frame, clk, din
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);
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parameter AW = 32;
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parameter PW = 2*AW+40;
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input frame;
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input clk;
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input [7:0] din;
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reg [3:0] cycle;
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reg read;
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reg [31:0] dstaddr;
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reg [31:0] srcaddr;
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reg [31:0] data;
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reg [3:0] ctrlmode;
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reg [1:0] datamode;
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reg burst;
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reg access;
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reg write;
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wire [103:0] packet;
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always @ (posedge clk)
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if(~frame)
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cycle[3:0] <= 'b0;
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else
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cycle[3:0] <= cycle[3:0]+1'b1;
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//Rising edge sampling
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always @ (posedge clk)
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if(frame)
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case (cycle)
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0:
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begin
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read <= din[7];
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burst <= din[2];
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end
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1:
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dstaddr[27:20] <= din[7:0];
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2:
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dstaddr[11:4] <= din[7:0];
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3:
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data[31:24] <= din[7:0];
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4:
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data[15:8] <= din[7:0];
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5:
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srcaddr[31:24] <= din[7:0];
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6:
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srcaddr[15:8] <= din[7:0];
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default:
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;
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endcase // case (cycle)
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//Falling edge sampling
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always @ (negedge clk)
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if(frame)
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case (cycle)
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1:
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begin
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ctrlmode[3:0] <= din[7:4];
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dstaddr[31:28] <= din[3:0];
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end
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2:
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dstaddr[19:12] <= din[7:0];
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3:
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begin
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dstaddr[3:0] <= din[7:4];
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datamode[1:0] <= din[3:2];
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write <= din[1];
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access <= din[0];
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end
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4:
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data[23:16] <= din[7:0];
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5:
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data[7:0] <= din[7:0];
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6:
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srcaddr[23:16] <= din[7:0];
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7:
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srcaddr[7:0] <= din[7:0];
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default: ;
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endcase // case (cycle)
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emesh2packet #(.AW(AW))
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e2p (
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// Outputs
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.packet_out (packet[PW-1:0]),
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// Inputs
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.write_out (write),
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.datamode_out (datamode[1:0]),
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.ctrlmode_out ({1'b0,ctrlmode[3:0]}),
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.dstaddr_out (dstaddr[AW-1:0]),
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.data_out (data[AW-1:0]),
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.srcaddr_out (srcaddr[AW-1:0]));
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endmodule // elink_monitor
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// Local Variables:
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// verilog-library-directories:("." "../hdl" "../../emesh/dv" "../../emesh/hdl")
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// End:
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