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127 lines
2.9 KiB
Verilog
127 lines
2.9 KiB
Verilog
module dut(/*AUTOARG*/
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// Outputs
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dut_active, clkout, wait_out, access_out, packet_out,
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// Inputs
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clk1, clk2, nreset, vdd, vss, access_in, packet_in, wait_in
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);
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parameter UREGS = 13;
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parameter AW = 32;
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parameter DW = 32;
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parameter CW = 2;
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parameter IDW = 12;
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parameter M_IDW = 6;
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parameter S_IDW = 12;
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parameter PW = 104;
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parameter N = 1;
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//#######################################
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//# CLOCK AND RESET
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//#######################################
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input clk1;
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input clk2;
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input nreset;
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input [N*N-1:0] vdd;
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input vss;
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output dut_active;
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output clkout;
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//#######################################
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//#EMESH INTERFACE
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//#######################################
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//Stimulus Driven Transaction
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input [N-1:0] access_in;
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input [N*PW-1:0] packet_in;
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output [N-1:0] wait_out;
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//DUT driven transaction
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output [N-1:0] access_out;
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output [N*PW-1:0] packet_out;
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input [N-1:0] wait_in;
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wire clk;
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire m_mosi; // From master of spi.v
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wire m_sclk; // From master of spi.v
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wire m_ss; // From master of spi.v
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wire s_miso; // From slave of spi.v
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wire spi_irq; // From master of spi.v, ...
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// End of automatics
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//###################
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// GLUE
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//###################
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assign clkout = clk1;
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assign clk = clk1;
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assign dut_active = 1'b1;
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//######################################################################
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//# DUT
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//######################################################################
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//drive through master, observe on slave
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spi #(.AW(AW),
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.UREGS(UREGS)
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)
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master (.m_miso (s_miso),
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.master_mode (1'b1),
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.s_miso (),
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.s_sclk (1'b0),
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.s_mosi (1'b0),
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.s_ss (1'b1),
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.wait_in (1'b0),
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.access_out (),
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.packet_out (),
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/*AUTOINST*/
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// Outputs
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.spi_irq (spi_irq),
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.wait_out (wait_out),
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.m_sclk (m_sclk),
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.m_mosi (m_mosi),
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.m_ss (m_ss),
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// Inputs
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.nreset (nreset),
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.clk (clk),
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.access_in (access_in),
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.packet_in (packet_in[PW-1:0]));
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spi #(.AW(AW),
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.UREGS(UREGS)
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)
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slave ( .s_sclk (m_sclk),
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.s_mosi (m_mosi),
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.s_ss (m_ss),
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.master_mode (1'b0),
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.access_in (1'b0),
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.packet_in (),
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.m_miso (),
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.m_sclk (),
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.m_mosi (),
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.m_ss (),
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.wait_out (),
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/*AUTOINST*/
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// Outputs
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.spi_irq (spi_irq),
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.access_out (access_out),
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.packet_out (packet_out[PW-1:0]),
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.s_miso (s_miso),
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// Inputs
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.nreset (nreset),
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.clk (clk),
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.wait_in (wait_in));
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endmodule // dut
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// Local Variables:
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// verilog-library-directories:("." "../hdl" "../../emesh/hdl")
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// End:
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