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40 lines
1.2 KiB
Verilog
40 lines
1.2 KiB
Verilog
//#############################################################################
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//# Function: Carry Save Adder (3:2) #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_csa32 #(parameter DW = 1 // data width
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)
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( input [DW-1:0] in0, //input
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input [DW-1:0] in1,//input
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input [DW-1:0] in2,//input
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output [DW-1:0] s, //sum
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output [DW-1:0] c //carry
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);
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localparam ASIC = `CFG_ASIC; // use asic library
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generate
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if(ASIC)
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begin : asic
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asic_csa32 i_csa32[DW-1:0] (.s(s[DW-1:0]),
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.c(c[DW-1:0]),
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.in2(in2[DW-1:0]),
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.in1(in1[DW-1:0]),
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.in0(in0[DW-1:0]));
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end
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else
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begin : generic
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assign s[DW-1:0] = in0[DW-1:0] ^ in1[DW-1:0] ^ in2[DW-1:0];
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assign c[DW-1:0] = (in0[DW-1:0] & in1[DW-1:0]) |
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(in1[DW-1:0] & in2[DW-1:0]) |
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(in2[DW-1:0] & in0[DW-1:0] );
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end
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endgenerate
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endmodule // oh_csa32
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