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77 lines
2.6 KiB
Verilog
77 lines
2.6 KiB
Verilog
//#############################################################################
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//# Function: Dual Port Memory #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_memory_dp # (parameter DW = 104, //memory width
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parameter DEPTH = 32, //memory depth
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parameter PROJ = "", //project name
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parameter MCW = 8, //repair/config vector width
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parameter AW = $clog2(DEPTH) // address bus width
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)
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(// Memory interface (dual port)
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input wr_clk, //write clock
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input wr_en, //write enable
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input [DW-1:0] wr_wem, //per bit write enable
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input [AW-1:0] wr_addr,//write address
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input [DW-1:0] wr_din, //write data
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input rd_clk, //read clock
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input rd_en, //read enable
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input [AW-1:0] rd_addr,//read address
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output [DW-1:0] rd_dout,//read output data
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// Power/repair (ASICs)
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input shutdown, // shutdown signal from always on domain
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input [MCW-1:0] memconfig, // generic memory config
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input [MCW-1:0] memrepair, // repair vector
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// BIST interface (ASICs)
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input bist_en, // bist enable
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input bist_we, // write enable global signal
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input [DW-1:0] bist_wem, // write enable vector
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input [AW-1:0] bist_addr, // address
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input [DW-1:0] bist_din // data input
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);
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localparam ASIC = `CFG_ASIC; // use asic library
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generate
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if(ASIC)
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begin : asic
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oh_memory_ram #(.DW(DW),
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.DEPTH(DEPTH))
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memory_dp (//read port
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.rd_dout (rd_dout[DW-1:0]),
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.rd_clk (rd_clk),
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.rd_en (rd_en),
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.rd_addr (rd_addr[AW-1:0]),
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//write port
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.wr_en (wr_en),
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.wr_clk (wr_clk),
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.wr_addr (wr_addr[AW-1:0]),
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.wr_wem (wr_wem[DW-1:0]),
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.wr_din (wr_din[DW-1:0]));
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end // if (ASIC)
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else
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begin : generic
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oh_memory_ram #(.DW(DW),
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.DEPTH(DEPTH))
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memory_dp (//read port
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.rd_dout (rd_dout[DW-1:0]),
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.rd_clk (rd_clk),
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.rd_en (rd_en),
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.rd_addr (rd_addr[AW-1:0]),
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//write port
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.wr_en (wr_en),
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.wr_clk (wr_clk),
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.wr_addr (wr_addr[AW-1:0]),
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.wr_wem (wr_wem[DW-1:0]),
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.wr_din (wr_din[DW-1:0]));
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end // else: !if(ASIC)
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endgenerate
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endmodule // oh_memory_dp
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