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b0b9315bf1
-this may break already broken projects -creates a Verilog top level (instead of using Vivado block level design) -integrates mmy and mailbox (not completely integrated) -compiles... -pours in all of the code from the archive (some new logic created)
15 lines
202 B
Batchfile
15 lines
202 B
Batchfile
dv_elink.v
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-y .
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-y ../../elink/hdl
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-y ../../stubs/hdl
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-y ../../common/hdl
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-y ../../axi/hdl
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-y ../../memory/hdl
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-y ../../embox/hdl
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-y ../../emmu/hdl
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-y ../../ecfg/hdl
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-y ../../erx/hdl
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-y ../../etx/hdl
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