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b0b9315bf1
-this may break already broken projects -creates a Verilog top level (instead of using Vivado block level design) -integrates mmy and mailbox (not completely integrated) -compiles... -pours in all of the code from the archive (some new logic created)
153 lines
5.2 KiB
Verilog
153 lines
5.2 KiB
Verilog
/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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/*###########################################################################
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# Function: A mailbox FIFO with a FIFO empty/full flags that can be used as
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# interrupts. Status of the FIFO can be polled.
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#
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# EMBOX0 = lower 32 bits of FIFO entry
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# EMBOX1 = upper 32 bits of FIFO entry
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# EMBSTATUS = status of FIFO [0]=1-->fifo not empty
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# [1]=1-->fifo full
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#
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# Notes: System takes care of not overflowing the FIFO
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# Reading the REG_EMBOX1 causes rd pointer to update to next entry
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# EMBOX0/EMBOX1 must be consecutive addresses for write.
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#
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############################################################################
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*/
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//Register Definitions
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`define EMBSTATUS 10'h019 //mailbox status
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`define EMBOX0 10'h01A //mailbox entry0 (read/write)
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`define EMBOX1 10'h01B //mailbox entry1 (read/write)
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module embox (/*AUTOARG*/
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// Outputs
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mi_dout, embox_full, embox_not_empty,
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// Inputs
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reset, clk, mi_en, mi_we, mi_addr, mi_din
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);
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parameter DW = 32; //data width of fifo
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parameter RFAW = 13; //address bus width
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parameter FAW = 4; //fifo entries==2^FAW
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/*****************************/
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/*CLOCK AND RESET */
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/*****************************/
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input reset; //synchronous reset
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input clk;
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/*****************************/
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/*SIMPLE MEMORY INTERFACE */
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/*****************************/
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input mi_en;
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input mi_we;
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input [RFAW-1:0] mi_addr;
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input [DW-1:0] mi_din;
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output [DW-1:0] mi_dout;
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/*****************************/
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/*MAILBOX OUTPUTS */
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/*****************************/
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output embox_full;
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output embox_not_empty;
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/*****************************/
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/*REGISTERS */
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/*****************************/
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reg [DW-1:0] mi_dout;
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reg [DW-1:0] embox_data_reg;
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reg mi_data_sel;
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/*****************************/
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/*WIRES */
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/*****************************/
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wire embox_w0_access;
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wire embox_w1_access;
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wire embox_status_access;
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wire embox_write;
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wire embox_w0_write;
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wire embox_w1_write;
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wire embox_read;
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wire embox_w0_read;
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wire embox_w1_read;
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wire embox_status_read;
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wire [DW-1:0] embox_read_data;
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wire [2*DW-1:0] embox_fifo_data;
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wire embox_empty;
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/*****************************/
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/*DECODE LOGIC */
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/*****************************/
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//access decode
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assign embox_w0_access = (mi_addr[RFAW-1:2]==`EMBOX0); //lower 32 bit word
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assign embox_w1_access = (mi_addr[RFAW-1:2]==`EMBOX1); //upper 32 bit word
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//fifo read/write logic
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assign embox_write = mi_en & mi_we;
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assign embox_w0_write = embox_w0_access & embox_write;
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assign embox_w1_write = embox_w1_access & embox_write; //causes FIFO write
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//read logic
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assign embox_read = mi_en & ~mi_we;
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assign embox_w1_read = embox_w1_access & embox_read; //causes FIFO read
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/*****************************/
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/*WRITE ACTION */
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/*****************************/
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//hold lower data word until upper word arrives
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always @ (posedge clk)
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if(embox_w0_write)
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embox_data_reg[DW-1:0] <=mi_din[DW-1:0];
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/*****************************/
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/*READ BACK DATA */
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/*****************************/
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always @ (posedge clk)
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if(embox_read)
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case(mi_addr[RFAW-1:2])
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`EMBOX0: mi_dout[DW-1:0] <= embox_fifo_data[DW-1:0];
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`EMBOX1: mi_dout[DW-1:0] <= embox_fifo_data[2*DW-1:DW];
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`EMBSTATUS: mi_dout[DW-1:0] <= {{(DW-2){1'b0}},embox_full,embox_not_empty};
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default: mi_dout[DW-1:0] <= 32'd0;
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endcase // case (mi_addr[RFAW-1:2])
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/*****************************/
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/*FIFO (64-BIT) */
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/*****************************/
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assign embox_not_empty = ~embox_empty;
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fifo_sync #(.DW(64)) mbox(// Outputs
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.rd_data (embox_fifo_data[2*DW-1:0]),
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.rd_empty (embox_empty),
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.wr_full (embox_full),
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// Inputs
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.rd_en (embox_w1_read),
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.wr_data ({mi_din[DW-1:0],embox_data_reg[DW-1:0]}),
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.wr_en (embox_w1_write),
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.clk (clk),
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.reset (reset)
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);
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endmodule // embox
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